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From: Peter Maydell <peter.maydell@linaro.org>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>,
	qemu-devel@nongnu.org, Paul Brook <paul@codesourcery.com>
Subject: [Qemu-devel] [PATCH 12/16] hw/omap.h: Drop broken MEM_VERBOSE tracing
Date: Tue, 19 Jun 2012 14:31:09 +0100	[thread overview]
Message-ID: <1340112673-14846-13-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1340112673-14846-1-git-send-email-peter.maydell@linaro.org>

Remove the MEM_VERBOSE tracing option from omap.h. This worked by
intercepting cpu_register_io_memory() calls; it has been broken
since cpu_register_io_memory() was removed in favour of the
MemoryRegion API.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/omap.h |   95 -------------------------------------------------------------
 1 files changed, 0 insertions(+), 95 deletions(-)

diff --git a/hw/omap.h b/hw/omap.h
index 2819e5d..3d98941 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -998,7 +998,6 @@ enum {
 #define OMAP_GPIOSW_OUTPUT	0x0002
 
 # define TCMI_VERBOSE			1
-//# define MEM_VERBOSE			1
 
 # ifdef TCMI_VERBOSE
 #  define OMAP_8B_REG(paddr)		\
@@ -1018,98 +1017,4 @@ enum {
 
 # define OMAP_MPUI_REG_MASK		0x000007ff
 
-# ifdef MEM_VERBOSE
-struct io_fn {
-    CPUReadMemoryFunc * const *mem_read;
-    CPUWriteMemoryFunc * const *mem_write;
-    void *opaque;
-    int in;
-};
-
-static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
-{
-    struct io_fn *s = opaque;
-    uint32_t ret;
-
-    s->in ++;
-    ret = s->mem_read[0](s->opaque, addr);
-    s->in --;
-    if (!s->in)
-        fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
-    return ret;
-}
-static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
-{
-    struct io_fn *s = opaque;
-    uint32_t ret;
-
-    s->in ++;
-    ret = s->mem_read[1](s->opaque, addr);
-    s->in --;
-    if (!s->in)
-        fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
-    return ret;
-}
-static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
-{
-    struct io_fn *s = opaque;
-    uint32_t ret;
-
-    s->in ++;
-    ret = s->mem_read[2](s->opaque, addr);
-    s->in --;
-    if (!s->in)
-        fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
-    return ret;
-}
-static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
-{
-    struct io_fn *s = opaque;
-
-    if (!s->in)
-        fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
-    s->in ++;
-    s->mem_write[0](s->opaque, addr, value);
-    s->in --;
-}
-static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
-{
-    struct io_fn *s = opaque;
-
-    if (!s->in)
-        fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
-    s->in ++;
-    s->mem_write[1](s->opaque, addr, value);
-    s->in --;
-}
-static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
-{
-    struct io_fn *s = opaque;
-
-    if (!s->in)
-        fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
-    s->in ++;
-    s->mem_write[2](s->opaque, addr, value);
-    s->in --;
-}
-
-static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw, };
-static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh, io_writew, };
-
-inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
-                                           CPUWriteMemoryFunc * const *mem_write,
-                                           void *opaque)
-{
-    struct io_fn *s = g_malloc(sizeof(struct io_fn));
-
-    s->mem_read = mem_read;
-    s->mem_write = mem_write;
-    s->opaque = opaque;
-    s->in = 0;
-    return cpu_register_io_memory(io_readfn, io_writefn, s,
-                                  DEVICE_NATIVE_ENDIAN);
-}
-#  define cpu_register_io_memory	debug_register_io_memory
-# endif
-
 #endif /* hw_omap_h */
-- 
1.7.1

  parent reply	other threads:[~2012-06-19 13:56 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-19 13:30 [Qemu-devel] [PULL 00/16] arm-devs queue Peter Maydell
2012-06-19 13:30 ` [Qemu-devel] [PATCH 01/16] ARM: Exynos4210 IRQ: Introduce new IRQ gate functionality Peter Maydell
2012-06-19 13:30 ` [Qemu-devel] [PATCH 02/16] arm_boot: Fix typos in comment Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 03/16] hw/arm_gic: Remove NVIC ifdefs from gic_state struct Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 04/16] hw/arm_gic: Remove the special casing of NCPU for the NVIC Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 05/16] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 06/16] hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 07/16] hw/arm_gic: Add qdev property for GIC revision Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 08/16] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 09/16] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 10/16] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 11/16] hw/armv7m_nvic: Make the NVIC a freestanding class Peter Maydell
2012-06-19 13:31 ` Peter Maydell [this message]
2012-06-19 13:31 ` [Qemu-devel] [PATCH 13/16] hw/a9mpcore: Fix compilation failure if physaddrs are 64 bit Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 14/16] cadence_gem: avoid stack-writing buffer-overrun Peter Maydell
2012-06-20  1:47   ` Peter Crosthwaite
2012-06-19 13:31 ` [Qemu-devel] [PATCH 15/16] cadence_ttc: changed master clock frequency Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 16/16] arm_boot: Conditionalised DTB command line update Peter Maydell
2012-06-24 12:26 ` [Qemu-devel] [PULL 00/16] arm-devs queue Blue Swirl

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