From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53079) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgyvS-0006yF-ES for qemu-devel@nongnu.org; Tue, 19 Jun 2012 09:57:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgyvI-00075s-AO for qemu-devel@nongnu.org; Tue, 19 Jun 2012 09:56:57 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:44844) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgyvI-00072F-0f for qemu-devel@nongnu.org; Tue, 19 Jun 2012 09:56:48 -0400 From: Peter Maydell Date: Tue, 19 Jun 2012 14:30:59 +0100 Message-Id: <1340112673-14846-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1340112673-14846-1-git-send-email-peter.maydell@linaro.org> References: <1340112673-14846-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 02/16] arm_boot: Fix typos in comment List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Anthony Liguori , qemu-devel@nongnu.org, Paul Brook From: Andreas Färber mimicing -> mimicking thei -> the Signed-off-by: Andreas Färber Reviewed-by: Stefan Weil Signed-off-by: Peter Maydell --- hw/arm-misc.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 1d51570..1f96229 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -45,9 +45,9 @@ struct arm_boot_info { /* multicore boards that use the default secondary core boot functions * can ignore these two function calls. If the default functions won't * work, then write_secondary_boot() should write a suitable blob of - * code mimicing the secondary CPU startup process used by the board's + * code mimicking the secondary CPU startup process used by the board's * boot loader/boot ROM code, and secondary_cpu_reset_hook() should - * perform any necessary CPU reset handling and set the PC for thei + * perform any necessary CPU reset handling and set the PC for the * secondary CPUs to point at this boot blob. */ void (*write_secondary_boot)(ARMCPU *cpu, -- 1.7.1