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From: Alexander Graf <agraf@suse.de>
To: qemu-devel qemu-devel <qemu-devel@nongnu.org>
Cc: Caraman Mihai Claudiu-B02008 <B02008@freescale.com>,
	qemu-ppc Mailing List <qemu-ppc@nongnu.org>
Subject: [Qemu-devel] [PATCH 4/8] PPC: Add some booke SPR defines
Date: Wed, 20 Jun 2012 22:11:47 +0200	[thread overview]
Message-ID: <1340223111-13449-5-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1340223111-13449-1-git-send-email-agraf@suse.de>

The number of SPRs avaiable in different PowerPC chip is still increasing. Add
definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/cpu.h |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 67e699c..12200ab 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1395,6 +1395,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
 #define SPR_BOOKE_TLB1PS      (0x159)
 #define SPR_BOOKE_TLB2PS      (0x15A)
 #define SPR_BOOKE_TLB3PS      (0x15B)
+#define SPR_BOOKE_MAS7_MAS3   (0x174)
 #define SPR_BOOKE_IVOR0       (0x190)
 #define SPR_BOOKE_IVOR1       (0x191)
 #define SPR_BOOKE_IVOR2       (0x192)
@@ -1762,6 +1763,27 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
 #define SPR_604_HID15         (0x3FF)
 #define SPR_E500_SVR          (0x3FF)
 
+/* Disable MAS Interrupt Updates for Hypervisor */
+#define EPCR_DMIUH            (1 << 22)
+/* Disable Guest TLB Management Instructions */
+#define EPCR_DGTMI            (1 << 23)
+/* Guest Interrupt Computation Mode */
+#define EPCR_GICM             (1 << 24)
+/* Interrupt Computation Mode */
+#define EPCR_ICM              (1 << 25)
+/* Disable Embedded Hypervisor Debug */
+#define EPCR_DUVD             (1 << 26)
+/* Instruction Storage Interrupt Directed to Guest State */
+#define EPCR_ISIGS            (1 << 27)
+/* Data Storage Interrupt Directed to Guest State */
+#define EPCR_DSIGS            (1 << 28)
+/* Instruction TLB Error Interrupt Directed to Guest State */
+#define EPCR_ITLBGS           (1 << 29)
+/* Data TLB Error Interrupt Directed to Guest State */
+#define EPCR_DTLBGS           (1 << 30)
+/* External Input Interrupt Directed to Guest State */
+#define EPCR_EXTGS            (1 << 31)
+
 /*****************************************************************************/
 /* PowerPC Instructions types definitions                                    */
 enum {
-- 
1.6.0.2

  parent reply	other threads:[~2012-06-20 20:12 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-20 20:11 [Qemu-devel] [PATCH 0/8] PPC: e5500 emulation Alexander Graf
2012-06-20 20:11 ` [Qemu-devel] [PATCH 1/8] dt: make setprop argument static Alexander Graf
2012-06-20 20:11 ` [Qemu-devel] [PATCH 2/8] PPC: e500: allow users to set the /compatible property via -machine Alexander Graf
2012-06-20 20:11 ` [Qemu-devel] [PATCH 3/8] uImage: increase the gzip load size Alexander Graf
2012-06-20 20:11 ` Alexander Graf [this message]
2012-06-20 20:11 ` [Qemu-devel] [PATCH 5/8] PPC: Add support for MSR_CM Alexander Graf
2012-06-20 20:11 ` [Qemu-devel] [PATCH 6/8] PPC: BookE: Implement EPR SPR Alexander Graf
2012-06-20 20:11 ` [Qemu-devel] [PATCH 7/8] PPC: Turn hardcoded reset mask into env variable Alexander Graf
2012-06-21 18:09   ` Blue Swirl
2012-06-21 19:04     ` Alexander Graf
2012-06-21 18:16   ` Peter Maydell
2012-06-20 20:11 ` [Qemu-devel] [PATCH 8/8] PPC: Add e5500 CPU target Alexander Graf
2012-06-20 22:26   ` Scott Wood
2012-06-20 22:59     ` Alexander Graf
2012-06-20 23:07       ` Scott Wood
2012-06-20 23:10         ` Alexander Graf
2012-06-20 23:28           ` Scott Wood

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