From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35994) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShXcG-0002zd-13 for qemu-devel@nongnu.org; Wed, 20 Jun 2012 22:59:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShXcE-0000IY-A1 for qemu-devel@nongnu.org; Wed, 20 Jun 2012 22:59:27 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:56427) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShXcE-0000Av-1d for qemu-devel@nongnu.org; Wed, 20 Jun 2012 22:59:26 -0400 Received: by mail-pz0-f45.google.com with SMTP id n2so221286dad.4 for ; Wed, 20 Jun 2012 19:59:25 -0700 (PDT) From: Jia Liu Date: Thu, 21 Jun 2012 10:58:01 +0800 Message-Id: <1340247488-10542-10-git-send-email-proljc@gmail.com> In-Reply-To: <1340247488-10542-1-git-send-email-proljc@gmail.com> References: <1340247488-10542-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH v6 09/16] target-or32: Add PIC support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Add OpenRISC Programmable Interrupt Controller support. Signed-off-by: Jia Liu --- hw/openrisc_pic.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c index 0d14bbe..76bd792 100644 --- a/hw/openrisc_pic.c +++ b/hw/openrisc_pic.c @@ -28,3 +28,51 @@ void cpu_openrisc_pic_reset(CPUOpenRISCState *env) env->picmr = 0x00000000; env->picsr = 0x00000000; } + +/* OpenRISC pic handler */ +static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) +{ + CPUOpenRISCState *env = (CPUOpenRISCState *)opaque; + int i; + uint32_t irq_bit = 1 << irq; + + if (irq > 31 || irq < 0) { + return; + } + + if (level) { + env->picsr |= irq_bit; + } else { + env->picsr &= ~irq_bit; + } + + for (i = 0; i < 32; i++) { + if ((env->picsr && (1 << i)) && (env->picmr && (1 << i))) { + cpu_interrupt(env, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + env->picsr &= ~(1 << i); + } + } +} + +void cpu_openrisc_pic_init(CPUOpenRISCState *env) +{ + int i; + qemu_irq *qi; + qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, env, NR_IRQS); + + for (i = 0; i < NR_IRQS; i++) { + env->irq[i] = qi[i]; + } +} + +void cpu_openrisc_store_picmr(CPUOpenRISCState *env, uint32_t value) +{ + env->picmr |= value; +} + +void cpu_openrisc_store_picsr(CPUOpenRISCState *env, uint32_t value) +{ + env->picsr &= ~value; +} -- 1.7.9.5