From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53823) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiEId-0005hs-Ox for qemu-devel@nongnu.org; Fri, 22 Jun 2012 20:34:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SiEIb-0007tA-Ty for qemu-devel@nongnu.org; Fri, 22 Jun 2012 20:34:03 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:36193) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiEIb-0007st-LM for qemu-devel@nongnu.org; Fri, 22 Jun 2012 20:34:01 -0400 Received: by pbbro12 with SMTP id ro12so4321638pbb.4 for ; Fri, 22 Jun 2012 17:33:59 -0700 (PDT) Sender: fluxion From: Michael Roth Date: Fri, 22 Jun 2012 19:33:08 -0500 Message-Id: <1340411610-22596-5-git-send-email-mdroth@linux.vnet.ibm.com> In-Reply-To: <1340411610-22596-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1340411610-22596-1-git-send-email-mdroth@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH stable-1.1 04/26] target-xtensa: extract TLB entry setting method List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com From: Max Filippov Signed-off-by: Max Filippov Signed-off-by: Blue Swirl --- target-xtensa/cpu.h | 3 +++ target-xtensa/op_helper.c | 15 +++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 6d0ea7c..6c590fe 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -370,6 +370,9 @@ void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, uint32_t *vpn, uint32_t wi, uint32_t *ei); int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, uint32_t *pwi, uint32_t *pei, uint8_t *pring); +void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, + xtensa_tlb_entry *entry, bool dtlb, + unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); int xtensa_get_physical_addr(CPUXtensaState *env, diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index ce61157..663bb6d 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -655,6 +655,16 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb) } } +void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, + xtensa_tlb_entry *entry, bool dtlb, + unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) +{ + entry->vaddr = vpn; + entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); + entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; + entry->attr = pte & 0xf; +} + void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) { @@ -665,10 +675,7 @@ void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, if (entry->asid) { tlb_flush_page(env, entry->vaddr); } - entry->vaddr = vpn; - entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); - entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; - entry->attr = pte & 0xf; + xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); tlb_flush_page(env, entry->vaddr); } else { qemu_log("%s %d, %d, %d trying to set immutable entry\n", -- 1.7.4.1