From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SoAnv-0002Xv-Lu for qemu-devel@nongnu.org; Mon, 09 Jul 2012 06:03:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SoAno-0006yG-Hy for qemu-devel@nongnu.org; Mon, 09 Jul 2012 06:02:55 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:57588) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SoAnn-0006xx-Sw for qemu-devel@nongnu.org; Mon, 09 Jul 2012 06:02:48 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 9 Jul 2012 12:02:28 +0200 Message-Id: <1341828152-15199-8-git-send-email-hpoussin@reactos.org> In-Reply-To: <1341828152-15199-1-git-send-email-hpoussin@reactos.org> References: <1341828152-15199-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 07/10] esp: split esp code into generic chip emulation and sysbus layer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Kevin Wolf Signed-off-by: Herv=C3=A9 Poussineau --- hw/esp.c | 162 ++++++++++++++++++++++++++++++++++++--------------------= ------ 1 file changed, 95 insertions(+), 67 deletions(-) diff --git a/hw/esp.c b/hw/esp.c index d9dd2aa..796cdc1 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -44,12 +44,9 @@ typedef struct ESPState ESPState; =20 struct ESPState { - SysBusDevice busdev; - MemoryRegion iomem; uint8_t rregs[ESP_REGS]; uint8_t wregs[ESP_REGS]; qemu_irq irq; - uint32_t it_shift; uint8_t chip_id; int32_t ti_size; uint32_t ti_rptr, ti_wptr; @@ -166,11 +163,8 @@ static void esp_lower_irq(ESPState *s) } } =20 -static void esp_dma_enable(void *opaque, int irq, int level) +static void esp_dma_enable(ESPState *s, int irq, int level) { - DeviceState *d =3D opaque; - ESPState *s =3D container_of(d, ESPState, busdev.qdev); - if (level) { s->dma_enabled =3D 1; trace_esp_dma_enable(); @@ -470,10 +464,8 @@ static void handle_ti(ESPState *s) } } =20 -static void esp_hard_reset(DeviceState *d) +static void esp_hard_reset(ESPState *s) { - ESPState *s =3D container_of(d, ESPState, busdev.qdev); - memset(s->rregs, 0, ESP_REGS); memset(s->wregs, 0, ESP_REGS); s->rregs[ESP_TCHI] =3D s->chip_id; @@ -487,40 +479,23 @@ static void esp_hard_reset(DeviceState *d) s->rregs[ESP_CFG1] =3D 7; } =20 -static void esp_soft_reset(DeviceState *d) +static void esp_soft_reset(ESPState *s) { - ESPState *s =3D container_of(d, ESPState, busdev.qdev); - qemu_irq_lower(s->irq); - esp_hard_reset(d); + esp_hard_reset(s); } =20 -static void parent_esp_reset(void *opaque, int irq, int level) +static void parent_esp_reset(ESPState *s, int irq, int level) { if (level) { - esp_soft_reset(opaque); + esp_soft_reset(s); } } =20 -static void esp_gpio_demux(void *opaque, int irq, int level) +static uint64_t esp_reg_read(ESPState *s, uint32_t saddr) { - switch (irq) { - case 0: - parent_esp_reset(opaque, irq, level); - break; - case 1: - esp_dma_enable(opaque, irq, level); - break; - } -} + uint32_t old_val; =20 -static uint64_t esp_mem_read(void *opaque, target_phys_addr_t addr, - unsigned size) -{ - ESPState *s =3D opaque; - uint32_t saddr, old_val; - - saddr =3D addr >> s->it_shift; trace_esp_mem_readb(saddr, s->rregs[saddr]); switch (saddr) { case ESP_FIFO: @@ -556,13 +531,8 @@ static uint64_t esp_mem_read(void *opaque, target_ph= ys_addr_t addr, return s->rregs[saddr]; } =20 -static void esp_mem_write(void *opaque, target_phys_addr_t addr, - uint64_t val, unsigned size) +static void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) { - ESPState *s =3D opaque; - uint32_t saddr; - - saddr =3D addr >> s->it_shift; trace_esp_mem_writeb(saddr, s->wregs[saddr], val); switch (saddr) { case ESP_TCLO: @@ -602,7 +572,7 @@ static void esp_mem_write(void *opaque, target_phys_a= ddr_t addr, break; case CMD_RESET: trace_esp_mem_writeb_cmd_reset(val); - esp_soft_reset(&s->busdev.qdev); + esp_soft_reset(s); break; case CMD_BUSRESET: trace_esp_mem_writeb_cmd_bus_reset(val); @@ -688,13 +658,6 @@ static bool esp_mem_accepts(void *opaque, target_phy= s_addr_t addr, return (size =3D=3D 1) || (is_write && size =3D=3D 4); } =20 -static const MemoryRegionOps esp_mem_ops =3D { - .read =3D esp_mem_read, - .write =3D esp_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid.accepts =3D esp_mem_accepts, -}; - static const VMStateDescription vmstate_esp =3D { .name =3D"esp", .version_id =3D 3, @@ -717,6 +680,40 @@ static const VMStateDescription vmstate_esp =3D { } }; =20 +typedef struct { + SysBusDevice busdev; + MemoryRegion iomem; + uint32_t it_shift; + ESPState esp; +} SysBusESPState; + +static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + uint32_t saddr; + + saddr =3D addr >> sysbus->it_shift; + esp_reg_write(&sysbus->esp, saddr, val); +} + +static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t add= r, + unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + uint32_t saddr; + + saddr =3D addr >> sysbus->it_shift; + return esp_reg_read(&sysbus->esp, saddr); +} + +static const MemoryRegionOps sysbus_esp_mem_ops =3D { + .read =3D sysbus_esp_mem_read, + .write =3D sysbus_esp_mem_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.accepts =3D esp_mem_accepts, +}; + void esp_init(target_phys_addr_t espaddr, int it_shift, ESPDMAMemoryReadWriteFunc dma_memory_read, ESPDMAMemoryReadWriteFunc dma_memory_write, @@ -725,14 +722,16 @@ void esp_init(target_phys_addr_t espaddr, int it_sh= ift, { DeviceState *dev; SysBusDevice *s; + SysBusESPState *sysbus; ESPState *esp; =20 dev =3D qdev_create(NULL, "esp"); - esp =3D DO_UPCAST(ESPState, busdev.qdev, dev); + sysbus =3D DO_UPCAST(SysBusESPState, busdev.qdev, dev); + esp =3D &sysbus->esp; esp->dma_memory_read =3D dma_memory_read; esp->dma_memory_write =3D dma_memory_write; esp->dma_opaque =3D dma_opaque; - esp->it_shift =3D it_shift; + sysbus->it_shift =3D it_shift; /* XXX for now until rc4030 has been changed to use DMA enable signa= l */ esp->dma_enabled =3D 1; qdev_init_nofail(dev); @@ -753,49 +752,78 @@ static const struct SCSIBusInfo esp_scsi_info =3D { .cancel =3D esp_request_cancelled }; =20 -static int esp_init1(SysBusDevice *dev) +static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) { - ESPState *s =3D FROM_SYSBUS(ESPState, dev); + DeviceState *d =3D opaque; + SysBusESPState *sysbus =3D container_of(d, SysBusESPState, busdev.qd= ev); + ESPState *s =3D &sysbus->esp; + + switch (irq) { + case 0: + parent_esp_reset(s, irq, level); + break; + case 1: + esp_dma_enable(opaque, irq, level); + break; + } +} + +static int sysbus_esp_init(SysBusDevice *dev) +{ + SysBusESPState *sysbus =3D FROM_SYSBUS(SysBusESPState, dev); + ESPState *s =3D &sysbus->esp; =20 sysbus_init_irq(dev, &s->irq); - assert(s->it_shift !=3D -1); + assert(sysbus->it_shift !=3D -1); =20 s->chip_id =3D TCHI_FAS100A; - memory_region_init_io(&s->iomem, &esp_mem_ops, s, - "esp", ESP_REGS << s->it_shift); - sysbus_init_mmio(dev, &s->iomem); + memory_region_init_io(&sysbus->iomem, &sysbus_esp_mem_ops, sysbus, + "esp", ESP_REGS << sysbus->it_shift); + sysbus_init_mmio(dev, &sysbus->iomem); =20 - qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2); + qdev_init_gpio_in(&dev->qdev, sysbus_esp_gpio_demux, 2); =20 scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info); return scsi_bus_legacy_handle_cmdline(&s->bus); } =20 -static Property esp_properties[] =3D { - {.name =3D NULL}, +static void sysbus_esp_hard_reset(DeviceState *dev) +{ + SysBusESPState *sysbus =3D DO_UPCAST(SysBusESPState, busdev.qdev, de= v); + esp_hard_reset(&sysbus->esp); +} + +static const VMStateDescription vmstate_sysbus_esp_scsi =3D { + .name =3D "sysbusespscsi", + .version_id =3D 0, + .minimum_version_id =3D 0, + .minimum_version_id_old =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), + VMSTATE_END_OF_LIST() + } }; =20 -static void esp_class_init(ObjectClass *klass, void *data) +static void sysbus_esp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); =20 - k->init =3D esp_init1; - dc->reset =3D esp_hard_reset; - dc->vmsd =3D &vmstate_esp; - dc->props =3D esp_properties; + k->init =3D sysbus_esp_init; + dc->reset =3D sysbus_esp_hard_reset; + dc->vmsd =3D &vmstate_sysbus_esp_scsi; } =20 -static TypeInfo esp_info =3D { +static TypeInfo sysbus_esp_info =3D { .name =3D "esp", .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(ESPState), - .class_init =3D esp_class_init, + .instance_size =3D sizeof(SysBusESPState), + .class_init =3D sysbus_esp_class_init, }; =20 static void esp_register_types(void) { - type_register_static(&esp_info); + type_register_static(&sysbus_esp_info); } =20 type_init(esp_register_types) --=20 1.7.10.4