From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpJa0-0002ie-0u for qemu-devel@nongnu.org; Thu, 12 Jul 2012 09:37:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SpJZx-0006rE-Ih for qemu-devel@nongnu.org; Thu, 12 Jul 2012 09:37:15 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:41606) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpJZx-0006no-Ai for qemu-devel@nongnu.org; Thu, 12 Jul 2012 09:37:13 -0400 From: Peter Maydell Date: Thu, 12 Jul 2012 14:36:55 +0100 Message-Id: <1342100216-1832-15-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1342100216-1832-1-git-send-email-peter.maydell@linaro.org> References: <1342100216-1832-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 14/15] target-arm: Implement TTBCR changes for LPAE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org, Anthony Liguori , Paul Brook Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it Signed-off-by: Peter Maydell --- target-arm/helper.c | 15 ++++++++++++++- 1 files changed, 14 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 110858d..72b44b0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -692,7 +692,20 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &= 7; + if (arm_feature(env, ARM_FEATURE_LPAE)) { + value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); + /* With LPAE the TTBCR could result in a change of ASID + * via the TTBCR.A1 bit, so do a TLB flush. + */ + tlb_flush(env, 1); + } else { + value &= 7; + } + /* Note that we always calculate c2_mask and c2_base_mask, but + * they are only used for short-descriptor tables (ie if EAE is 0); + * for long-descriptor tables the TTBCR fields are used differently + * and the c2_mask and c2_base_mask values are meaningless. + */ env->cp15.c2_control = value; env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value); env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value); -- 1.7.1