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From: Peter Maydell <peter.maydell@linaro.org>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: qemu-devel@nongnu.org, Anthony Liguori <anthony@codemonkey.ws>,
	Paul Brook <paul@codesourcery.com>
Subject: [Qemu-devel] [PATCH 01/15] target-arm: Fix CP15 based WFI
Date: Thu, 12 Jul 2012 14:36:42 +0100	[thread overview]
Message-ID: <1342100216-1832-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1342100216-1832-1-git-send-email-peter.maydell@linaro.org>

From: Paul Brook <paul@codesourcery.com>

The coprocessor register rework broke cp15 based WFI instructions.
We incorrectly fall through the normal register write case, which
incorrectly adds a forced block termination.  We've already done
a special version of this (DISAS_WFI), so return immediately.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index a2a0ecd..f39b9ca 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6236,7 +6236,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
             }
             gen_set_pc_im(s->pc);
             s->is_jmp = DISAS_WFI;
-            break;
+            return 0;
         default:
             break;
         }
-- 
1.7.1

  reply	other threads:[~2012-07-12 13:37 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-12 13:36 [Qemu-devel] [PULL 00/15] target-arm queue Peter Maydell
2012-07-12 13:36 ` Peter Maydell [this message]
2012-07-12 13:36 ` [Qemu-devel] [PATCH 02/15] target-arm: Fix typo that meant TTBR1 accesses went to TTBR0 Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 03/15] target-arm: Fix some copy-and-paste errors in cp register names Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 04/15] target-arm: Fix TCG temp handling in 64 bit cp writes Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 05/15] hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 06/15] ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits Peter Maydell
2012-09-05 22:44   ` Jan Kiszka
2012-07-12 13:36 ` [Qemu-devel] [PATCH 07/15] target-arm: Implement privileged-execute-never (PXN) Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 08/15] target-arm: Extend feature flags to 64 bits Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 09/15] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 10/15] target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 11/15] target-arm: Add 64 bit PAR, TTBR0, TTBR1 " Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 12/15] target-arm: Use target_phys_addr_t in get_phys_addr() Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 13/15] target-arm: Implement long-descriptor PAR format Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 14/15] target-arm: Implement TTBCR changes for LPAE Peter Maydell
2012-07-12 13:36 ` [Qemu-devel] [PATCH 15/15] target-arm: Add support for long format translation table walks Peter Maydell
2012-07-14 12:21 ` [Qemu-devel] [PULL 00/15] target-arm queue Blue Swirl

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