From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:44195) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SqlHt-0004rx-RQ for qemu-devel@nongnu.org; Mon, 16 Jul 2012 09:24:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SqlHp-0001P4-EP for qemu-devel@nongnu.org; Mon, 16 Jul 2012 09:24:33 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:44364) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SqlHp-0001NI-7C for qemu-devel@nongnu.org; Mon, 16 Jul 2012 09:24:29 -0400 From: Peter Maydell Date: Mon, 16 Jul 2012 14:24:15 +0100 Message-Id: <1342445056-9129-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1342445056-9129-1-git-send-email-peter.maydell@linaro.org> References: <1342445056-9129-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 5/6] hw/arm_boot.c: Support DTBs which use 64 bit addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org Support the case where the device tree blob specifies that #address-cells and #size-cells are greater than 1. (This is needed for device trees which can handle 64 bit physical addresses and thus total RAM sizes over 4GB.) Signed-off-by: Peter Maydell Reviewed-by: Peter A. G. Crosthwaite --- hw/arm_boot.c | 35 ++++++++++++++++++++++++++++++++--- 1 files changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/arm_boot.c b/hw/arm_boot.c index af71ed6..a6e9143 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -216,11 +216,12 @@ static void set_kernel_args_old(const struct arm_boot_info *info) static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) { #ifdef CONFIG_FDT - uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start), - cpu_to_be32(binfo->ram_size) }; + uint32_t *mem_reg_property; + uint32_t mem_reg_propsize; void *fdt = NULL; char *filename; int size, rc; + uint32_t acells, scells, hival; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); if (!filename) { @@ -236,8 +237,36 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) } g_free(filename); + acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells"); + scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells"); + if (acells == 0 || scells == 0) { + fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); + return -1; + } + + mem_reg_propsize = acells + scells; + mem_reg_property = g_new0(uint32_t, mem_reg_propsize); + mem_reg_property[acells - 1] = cpu_to_be32(binfo->loader_start); + hival = cpu_to_be32(binfo->loader_start >> 32); + if (acells > 1) { + mem_reg_property[acells - 2] = hival; + } else if (hival != 0) { + fprintf(stderr, "qemu: dtb file not compatible with " + "RAM start address > 4GB\n"); + exit(1); + } + mem_reg_property[acells + scells - 1] = cpu_to_be32(binfo->ram_size); + hival = cpu_to_be32(binfo->ram_size >> 32); + if (scells > 1) { + mem_reg_property[acells + scells - 2] = hival; + } else if (hival != 0) { + fprintf(stderr, "qemu: dtb file not compatible with " + "RAM size > 4GB\n"); + exit(1); + } + rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, - sizeof(mem_reg_property)); + mem_reg_propsize * sizeof(uint32_t)); if (rc < 0) { fprintf(stderr, "couldn't set /memory/reg\n"); } -- 1.7.5.4