From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sr6vq-000215-Ps for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:31:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sr6vg-0007og-Oq for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:31:14 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34752) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sr6vg-0007oE-FG for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:31:04 -0400 From: Gerd Hoffmann Date: Tue, 17 Jul 2012 14:31:02 +0200 Message-Id: <1342528262-11548-4-git-send-email-kraxel@redhat.com> In-Reply-To: <1342528262-11548-1-git-send-email-kraxel@redhat.com> References: <1342528262-11548-1-git-send-email-kraxel@redhat.com> Subject: [Qemu-devel] [rfc patch seabios 3/3] wakeup: uhci List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, seabios@seabios.org Cc: Gerd Hoffmann Windup gpe bit 0x0b for s3 wakeup. Also add methods to update the pci config space register 0xc4 which enables/disables wakeup per usb port. Signed-off-by: Gerd Hoffmann --- src/acpi-dsdt.dsl | 41 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index 03efbfd..07e531d 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -312,6 +312,46 @@ DefinitionBlock ( /**************************************************************** + * USB + ****************************************************************/ + + Scope(\_SB.PCI0) { + Device (UHCI) { + Name (_ADR, 0x00010002) + + OperationRegion (U0CS, PCI_Config, 0xC4, 0x04) + Field (U0CS, DWordAcc, NoLock, Preserve) + { + U0EN, 2, + Offset (0x04) + } + + Name (_S3D, 0x03) + Name (_S3W, 0x03) + + /* Power Resources for Wake */ + Name(_PRW, Package(2) { + 0x0b, // GPE bit + 0x03, // S3 + }) + + /* Power State Wake */ + Method (_PSW, 1, NotSerialized) + { + If (Arg0) + { + Store (0x03, U0EN) + } + Else + { + Store (0x00, U0EN) + } + } + } + } + + +/**************************************************************** * PIIX3 ISA bridge ****************************************************************/ @@ -803,6 +843,7 @@ DefinitionBlock ( Return(0x01) } Method(_L0B) { + Notify(\_SB.PCI0.UHCI, 0x80) Return(0x01) } Method(_L0C) { -- 1.7.1