From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SwkVX-0004Bw-LR for qemu-devel@nongnu.org; Wed, 01 Aug 2012 21:47:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SwkVU-0000Dl-BB for qemu-devel@nongnu.org; Wed, 01 Aug 2012 21:47:23 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34358 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SwkVT-0000DL-F9 for qemu-devel@nongnu.org; Wed, 01 Aug 2012 21:47:20 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 2 Aug 2012 03:46:55 +0200 Message-Id: <1343872026-18189-4-git-send-email-afaerber@suse.de> In-Reply-To: <1343872026-18189-1-git-send-email-afaerber@suse.de> References: <1343872026-18189-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH for-1.2 v5 03/14] bonito: QOM'ify Bonito PCI host bridge List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , anthony@codemonkey.ws, mst@redhat.com Introduce type constant. Avoid accessing DeviceState or SysBusDevice indirectly through PCIHostState field. Drop global state by passing BonitoState as opaque and adding the IRQs and a pointer to PCIBonitoState to its state. Signed-off-by: Andreas F=C3=A4rber --- hw/bonito.c | 146 ++++++++++++++++++++++++++++++++++++-----------------= ------ 1 files changed, 90 insertions(+), 56 deletions(-) diff --git a/hw/bonito.c b/hw/bonito.c index b990875..062c701 100644 --- a/hw/bonito.c +++ b/hw/bonito.c @@ -180,11 +180,14 @@ #define PCI_ADDR(busno,devno,funno,regno) \ ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0= x700) + (regno)) =20 -typedef PCIHostState BonitoState; +#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" + +typedef struct BonitoState BonitoState; =20 typedef struct PCIBonitoState { PCIDevice dev; + BonitoState *pcihost; uint32_t regs[BONITO_REGS]; =20 @@ -218,7 +221,16 @@ typedef struct PCIBonitoState =20 } PCIBonitoState; =20 -PCIBonitoState * bonito_state; +#define BONITO_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) + +struct BonitoState { + PCIHostState parent_obj; + + qemu_irq *pic; + + PCIBonitoState *pci_dev; +}; =20 static void bonito_writel(void *opaque, target_phys_addr_t addr, uint64_t val, unsigned size) @@ -314,9 +326,10 @@ static void bonito_pciconf_writel(void *opaque, targ= et_phys_addr_t addr, uint64_t val, unsigned size) { PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); =20 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val= ); - s->dev.config_write(&s->dev, addr, val, 4); + d->config_write(d, addr, val, 4); } =20 static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t ad= dr, @@ -324,9 +337,10 @@ static uint64_t bonito_pciconf_readl(void *opaque, t= arget_phys_addr_t addr, { =20 PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); =20 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); - return s->dev.config_read(&s->dev, addr, 4); + return d->config_read(d, addr, 4); } =20 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ @@ -402,6 +416,7 @@ static const MemoryRegionOps bonito_cop_ops =3D { static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t = addr) { PCIBonitoState *s =3D opaque; + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pc= ihost)); uint32_t cfgaddr; uint32_t idsel; uint32_t devno; @@ -423,13 +438,13 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque= , target_phys_addr_t addr) regno =3D (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_= OFFSET; =20 if (idsel =3D=3D 0) { - fprintf(stderr, "error in bonito pci config address" TARGET_FMT_= plx + fprintf(stderr, "error in bonito pci config address " TARGET_FMT= _plx ",pcimap_cfg=3D%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); exit(1); } - pciaddr =3D PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, reg= no); + pciaddr =3D PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n= ", - cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, re= gno); + cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); =20 return pciaddr; } @@ -438,6 +453,8 @@ static void bonito_spciconf_writeb(void *opaque, targ= et_phys_addr_t addr, uint32_t val) { PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pc= ihost)); uint32_t pciaddr; uint16_t status; =20 @@ -449,24 +466,26 @@ static void bonito_spciconf_writeb(void *opaque, ta= rget_phys_addr_t addr, } =20 /* set the pci address in s->config_reg */ - s->pcihost->config_reg =3D (pciaddr) | (1u << 31); - pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, = 1); + phb->config_reg =3D (pciaddr) | (1u << 31); + pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1); =20 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT= */ - status =3D pci_get_word(s->dev.config + PCI_STATUS); + status =3D pci_get_word(d->config + PCI_STATUS); status &=3D ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_AB= ORT); - pci_set_word(s->dev.config + PCI_STATUS, status); + pci_set_word(d->config + PCI_STATUS, status); } =20 static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr= , uint32_t val) { PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pc= ihost)); uint32_t pciaddr; uint16_t status; =20 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, va= l); - assert((addr&0x1)=3D=3D0); + assert((addr & 0x1) =3D=3D 0); =20 pciaddr =3D bonito_sbridge_pciaddr(s, addr); =20 @@ -475,24 +494,26 @@ static void bonito_spciconf_writew(void *opaque, ta= rget_phys_addr_t addr, } =20 /* set the pci address in s->config_reg */ - s->pcihost->config_reg =3D (pciaddr) | (1u << 31); - pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2); + phb->config_reg =3D (pciaddr) | (1u << 31); + pci_data_write(phb->bus, phb->config_reg, val, 2); =20 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT= */ - status =3D pci_get_word(s->dev.config + PCI_STATUS); + status =3D pci_get_word(d->config + PCI_STATUS); status &=3D ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_AB= ORT); - pci_set_word(s->dev.config + PCI_STATUS, status); + pci_set_word(d->config + PCI_STATUS, status); } =20 static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr= , uint32_t val) { PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pc= ihost)); uint32_t pciaddr; uint16_t status; =20 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, va= l); - assert((addr&0x3)=3D=3D0); + assert((addr & 0x3) =3D=3D 0); =20 pciaddr =3D bonito_sbridge_pciaddr(s, addr); =20 @@ -501,18 +522,20 @@ static void bonito_spciconf_writel(void *opaque, ta= rget_phys_addr_t addr, } =20 /* set the pci address in s->config_reg */ - s->pcihost->config_reg =3D (pciaddr) | (1u << 31); - pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4); + phb->config_reg =3D (pciaddr) | (1u << 31); + pci_data_write(phb->bus, phb->config_reg, val, 4); =20 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT= */ - status =3D pci_get_word(s->dev.config + PCI_STATUS); + status =3D pci_get_word(d->config + PCI_STATUS); status &=3D ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_AB= ORT); - pci_set_word(s->dev.config + PCI_STATUS, status); + pci_set_word(d->config + PCI_STATUS, status); } =20 static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t a= ddr) { PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pc= ihost)); uint32_t pciaddr; uint16_t status; =20 @@ -524,24 +547,26 @@ static uint32_t bonito_spciconf_readb(void *opaque,= target_phys_addr_t addr) } =20 /* set the pci address in s->config_reg */ - s->pcihost->config_reg =3D (pciaddr) | (1u << 31); + phb->config_reg =3D (pciaddr) | (1u << 31); =20 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT= */ - status =3D pci_get_word(s->dev.config + PCI_STATUS); + status =3D pci_get_word(d->config + PCI_STATUS); status &=3D ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_AB= ORT); - pci_set_word(s->dev.config + PCI_STATUS, status); + pci_set_word(d->config + PCI_STATUS, status); =20 - return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1); + return pci_data_read(phb->bus, phb->config_reg, 1); } =20 static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t a= ddr) { PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pc= ihost)); uint32_t pciaddr; uint16_t status; =20 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); - assert((addr&0x1)=3D=3D0); + assert((addr & 0x1) =3D=3D 0); =20 pciaddr =3D bonito_sbridge_pciaddr(s, addr); =20 @@ -550,24 +575,26 @@ static uint32_t bonito_spciconf_readw(void *opaque,= target_phys_addr_t addr) } =20 /* set the pci address in s->config_reg */ - s->pcihost->config_reg =3D (pciaddr) | (1u << 31); + phb->config_reg =3D (pciaddr) | (1u << 31); =20 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT= */ - status =3D pci_get_word(s->dev.config + PCI_STATUS); + status =3D pci_get_word(d->config + PCI_STATUS); status &=3D ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_AB= ORT); - pci_set_word(s->dev.config + PCI_STATUS, status); + pci_set_word(d->config + PCI_STATUS, status); =20 - return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2); + return pci_data_read(phb->bus, phb->config_reg, 2); } =20 static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t a= ddr) { PCIBonitoState *s =3D opaque; + PCIDevice *d =3D PCI_DEVICE(s); + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pc= ihost)); uint32_t pciaddr; uint16_t status; =20 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); - assert((addr&0x3) =3D=3D 0); + assert((addr & 0x3) =3D=3D 0); =20 pciaddr =3D bonito_sbridge_pciaddr(s, addr); =20 @@ -576,14 +603,14 @@ static uint32_t bonito_spciconf_readl(void *opaque,= target_phys_addr_t addr) } =20 /* set the pci address in s->config_reg */ - s->pcihost->config_reg =3D (pciaddr) | (1u << 31); + phb->config_reg =3D (pciaddr) | (1u << 31); =20 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT= */ - status =3D pci_get_word(s->dev.config + PCI_STATUS); + status =3D pci_get_word(d->config + PCI_STATUS); status &=3D ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_AB= ORT); - pci_set_word(s->dev.config + PCI_STATUS, status); + pci_set_word(d->config + PCI_STATUS, status); =20 - return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4); + return pci_data_read(phb->bus, phb->config_reg, 4); } =20 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ @@ -607,13 +634,15 @@ static const MemoryRegionOps bonito_spciconf_ops =3D= { =20 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) { - qemu_irq *pic =3D opaque; + BonitoState *s =3D opaque; + qemu_irq *pic =3D s->pic; + PCIBonitoState *bonito_state =3D s->pci_dev; int internal_irq =3D irq_num - BONITO_IRQ_BASE; =20 - if (bonito_state->regs[BONITO_INTEDGE] & (1<regs[BONITO_INTEDGE] & (1 << internal_irq)) { qemu_irq_pulse(*pic); } else { /* level triggered */ - if (bonito_state->regs[BONITO_INTPOL] & (1<regs[BONITO_INTPOL] & (1 << internal_irq)) { qemu_irq_raise(*pic); } else { qemu_irq_lower(*pic); @@ -673,13 +702,21 @@ static const VMStateDescription vmstate_bonito =3D = { =20 static int bonito_pcihost_initfn(SysBusDevice *dev) { + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, dev); + + phb->bus =3D pci_register_bus(DEVICE(dev), "pci", + pci_bonito_set_irq, pci_bonito_map_irq, = dev, + get_system_memory(), get_system_io(), + 0x28, 32); + return 0; } =20 static int bonito_initfn(PCIDevice *dev) { PCIBonitoState *s =3D DO_UPCAST(PCIBonitoState, dev, dev); - SysBusDevice *sysbus =3D &s->pcihost->busdev; + SysBusDevice *sysbus =3D SYS_BUS_DEVICE(s->pcihost); + PCIHostState *phb =3D FROM_SYSBUS(PCIHostState, sysbus); =20 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "unde= fined" */ pci_config_set_prog_interface(dev->config, 0x00); @@ -691,15 +728,15 @@ static int bonito_initfn(PCIDevice *dev) sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); =20 /* set the north bridge pci configure mapping */ - memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s, + memory_region_init_io(&phb->conf_mem, &bonito_pciconf_ops, s, "north-bridge-pci-config", BONITO_PCICONFIG_SI= ZE); - sysbus_init_mmio(sysbus, &s->pcihost->conf_mem); + sysbus_init_mmio(sysbus, &phb->conf_mem); sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); =20 /* set the south bridge pci configure mapping */ - memory_region_init_io(&s->pcihost->data_mem, &bonito_spciconf_ops, s= , + memory_region_init_io(&phb->data_mem, &bonito_spciconf_ops, s, "south-bridge-pci-config", BONITO_SPCICONFIG_S= IZE); - sysbus_init_mmio(sysbus, &s->pcihost->data_mem); + sysbus_init_mmio(sysbus, &phb->data_mem); sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); =20 memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s, @@ -742,28 +779,25 @@ static int bonito_initfn(PCIDevice *dev) PCIBus *bonito_init(qemu_irq *pic) { DeviceState *dev; - PCIBus *b; BonitoState *pcihost; + PCIHostState *phb; PCIBonitoState *s; PCIDevice *d; =20 - dev =3D qdev_create(NULL, "Bonito-pcihost"); - pcihost =3D FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev)); - b =3D pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_= irq, - pci_bonito_map_irq, pic, get_system_memory(), - get_system_io(), - 0x28, 32); - pcihost->bus =3D b; + dev =3D qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); + phb =3D FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); + pcihost =3D BONITO_PCI_HOST_BRIDGE(dev); + pcihost->pic =3D pic; qdev_init_nofail(dev); =20 /* set the pcihost pointer before bonito_initfn is called */ - d =3D pci_create(b, PCI_DEVFN(0, 0), "Bonito"); + d =3D pci_create(phb->bus, PCI_DEVFN(0, 0), "Bonito"); s =3D DO_UPCAST(PCIBonitoState, dev, d); s->pcihost =3D pcihost; - bonito_state =3D s; - qdev_init_nofail(&d->qdev); + pcihost->pci_dev =3D s; + qdev_init_nofail(DEVICE(d)); =20 - return b; + return phb->bus; } =20 static void bonito_class_init(ObjectClass *klass, void *data) @@ -798,7 +832,7 @@ static void bonito_pcihost_class_init(ObjectClass *kl= ass, void *data) } =20 static const TypeInfo bonito_pcihost_info =3D { - .name =3D "Bonito-pcihost", + .name =3D TYPE_BONITO_PCI_HOST_BRIDGE, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(BonitoState), .class_init =3D bonito_pcihost_class_init, --=20 1.7.7