From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SxjjB-0002aV-HR for qemu-devel@nongnu.org; Sat, 04 Aug 2012 15:09:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sxjj8-0000Dc-CS for qemu-devel@nongnu.org; Sat, 04 Aug 2012 15:09:33 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:55077) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sxjj7-0000D7-Kx for qemu-devel@nongnu.org; Sat, 04 Aug 2012 15:09:30 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sat, 4 Aug 2012 21:10:04 +0200 Message-Id: <1344107406-27608-3-git-send-email-hpoussin@reactos.org> In-Reply-To: <1344107406-27608-1-git-send-email-hpoussin@reactos.org> References: <1344107406-27608-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 2/4] esp: move PCI emulation to a new file esp-pci.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Paolo Bonzini , =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Anthony Liguori sparc machines loose ability to instanciate PCI ESP SCSI adapter, which is not a big loose as they don't have PCI bus support. Signed-off-by: Herv=C3=A9 Poussineau --- default-configs/pci.mak | 1 + hw/Makefile.objs | 1 + hw/esp-pci.c | 396 +++++++++++++++++++++++++++++++++++++++++= ++++++ hw/esp.c | 362 -----------------------------------------= -- 4 files changed, 398 insertions(+), 362 deletions(-) create mode 100644 hw/esp-pci.c diff --git a/default-configs/pci.mak b/default-configs/pci.mak index 9febb47..69e18f1 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -18,3 +18,4 @@ CONFIG_IDE_QDEV=3Dy CONFIG_IDE_PCI=3Dy CONFIG_AHCI=3Dy CONFIG_ESP=3Dy +CONFIG_ESP_PCI=3Dy diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 8327e55..12cc141 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -88,6 +88,7 @@ hw-obj-$(CONFIG_OPENCORES_ETH) +=3D opencores_eth.o hw-obj-$(CONFIG_LSI_SCSI_PCI) +=3D lsi53c895a.o hw-obj-$(CONFIG_MEGASAS_SCSI_PCI) +=3D megasas.o hw-obj-$(CONFIG_ESP) +=3D esp.o +hw-obj-$(CONFIG_ESP_PCI) +=3D esp-pci.o =20 hw-obj-y +=3D sysbus.o isa-bus.o hw-obj-y +=3D qdev-addr.o diff --git a/hw/esp-pci.c b/hw/esp-pci.c new file mode 100644 index 0000000..f633a18 --- /dev/null +++ b/hw/esp-pci.c @@ -0,0 +1,396 @@ +/* + * QEMU ESP/NCR53C9x emulation + * + * Copyright (c) 2005-2006 Fabrice Bellard + * Copyright (c) 2012 Herve Poussineau + * + * Permission is hereby granted, free of charge, to any person obtaining= a copy + * of this software and associated documentation files (the "Software"),= to deal + * in the Software without restriction, including without limitation the= rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or = sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be includ= ed in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S IN + * THE SOFTWARE. + */ + +#include "pci.h" +#include "esp.h" +#include "trace.h" +#include "qemu-log.h" + +#define DMA_CMD 0x0 +#define DMA_STC 0x1 +#define DMA_SPA 0x2 +#define DMA_WBC 0x3 +#define DMA_WAC 0x4 +#define DMA_STAT 0x5 +#define DMA_SMDLA 0x6 +#define DMA_WMAC 0x7 + +#define DMA_CMD_MASK 0x03 +#define DMA_CMD_DIAG 0x04 +#define DMA_CMD_MDL 0x10 +#define DMA_CMD_INTE_P 0x20 +#define DMA_CMD_INTE_D 0x40 +#define DMA_CMD_DIR 0x80 + +#define DMA_STAT_PWDN 0x01 +#define DMA_STAT_ERROR 0x02 +#define DMA_STAT_ABORT 0x04 +#define DMA_STAT_DONE 0x08 +#define DMA_STAT_SCSIINT 0x10 +#define DMA_STAT_BCMBLT 0x20 + +#define SBAC_STATUS 0x1000 + +typedef struct PCIESPState { + PCIDevice dev; + MemoryRegion io; + uint32_t dma_regs[8]; + uint32_t sbac; + ESPState esp; +} PCIESPState; + +static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) +{ + trace_esp_pci_dma_idle(val); + esp_dma_enable(&pci->esp, 0, 0); +} + +static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) +{ + trace_esp_pci_dma_blast(val); + qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n"); +} + +static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) +{ + trace_esp_pci_dma_abort(val); + if (pci->esp.current_req) { + scsi_req_cancel(pci->esp.current_req); + } +} + +static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) +{ + trace_esp_pci_dma_start(val); + + pci->dma_regs[DMA_WBC] =3D pci->dma_regs[DMA_STC]; + pci->dma_regs[DMA_WAC] =3D pci->dma_regs[DMA_SPA]; + pci->dma_regs[DMA_WMAC] =3D pci->dma_regs[DMA_SMDLA]; + + pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT + | DMA_STAT_DONE | DMA_STAT_ABORT + | DMA_STAT_ERROR | DMA_STAT_PWDN); + + esp_dma_enable(&pci->esp, 0, 1); +} + +static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t= val) +{ + trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val); + switch (saddr) { + case DMA_CMD: + pci->dma_regs[saddr] =3D val; + switch (val & DMA_CMD_MASK) { + case 0x0: /* IDLE */ + esp_pci_handle_idle(pci, val); + break; + case 0x1: /* BLAST */ + esp_pci_handle_blast(pci, val); + break; + case 0x2: /* ABORT */ + esp_pci_handle_abort(pci, val); + break; + case 0x3: /* START */ + esp_pci_handle_start(pci, val); + break; + default: /* can't happen */ + abort(); + } + break; + case DMA_STC: + case DMA_SPA: + case DMA_SMDLA: + pci->dma_regs[saddr] =3D val; + break; + case DMA_STAT: + if (!(pci->sbac & SBAC_STATUS)) { + /* clear some bits on write */ + uint32_t mask =3D DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT= _DONE; + pci->dma_regs[DMA_STAT] &=3D ~(val & mask); + } + break; + default: + trace_esp_pci_error_invalid_write_dma(val, saddr); + return; + } +} + +static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) +{ + uint32_t val; + + val =3D pci->dma_regs[saddr]; + if (saddr =3D=3D DMA_STAT) { + if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { + val |=3D DMA_STAT_SCSIINT; + } + if (pci->sbac & SBAC_STATUS) { + pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_ERROR | DMA_STAT_ABO= RT | + DMA_STAT_DONE); + } + } + + trace_esp_pci_dma_read(saddr, val); + return val; +} + +static void esp_pci_io_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned int size) +{ + PCIESPState *pci =3D opaque; + + if (size < 4 || addr & 3) { + /* need to upgrade request: we only support 4-bytes accesses */ + uint32_t current =3D 0, mask; + int shift; + + if (addr < 0x40) { + current =3D pci->esp.wregs[addr >> 2]; + } else if (addr < 0x60) { + current =3D pci->dma_regs[(addr - 0x40) >> 2]; + } else if (addr < 0x74) { + current =3D pci->sbac; + } + + shift =3D (4 - size) * 8; + mask =3D (~(uint32_t)0 << shift) >> shift; + + shift =3D ((4 - (addr & 3)) & 3) * 8; + val <<=3D shift; + val |=3D current & ~(mask << shift); + addr &=3D ~3; + size =3D 4; + } + + if (addr < 0x40) { + /* SCSI core reg */ + esp_reg_write(&pci->esp, addr >> 2, val); + } else if (addr < 0x60) { + /* PCI DMA CCB */ + esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); + } else if (addr =3D=3D 0x70) { + /* DMA SCSI Bus and control */ + trace_esp_pci_sbac_write(pci->sbac, val); + pci->sbac =3D val; + } else { + trace_esp_pci_error_invalid_write((int)addr); + } +} + +static uint64_t esp_pci_io_read(void *opaque, target_phys_addr_t addr, + unsigned int size) +{ + PCIESPState *pci =3D opaque; + uint32_t ret; + + if (addr < 0x40) { + /* SCSI core reg */ + ret =3D esp_reg_read(&pci->esp, addr >> 2); + } else if (addr < 0x60) { + /* PCI DMA CCB */ + ret =3D esp_pci_dma_read(pci, (addr - 0x40) >> 2); + } else if (addr =3D=3D 0x70) { + /* DMA SCSI Bus and control */ + trace_esp_pci_sbac_read(pci->sbac); + ret =3D pci->sbac; + } else { + /* Invalid region */ + trace_esp_pci_error_invalid_read((int)addr); + ret =3D 0; + } + + /* give only requested data */ + ret >>=3D (addr & 3) * 8; + ret &=3D ~(~(uint64_t)0 << (8 * size)); + + return ret; +} + +static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int le= n, + DMADirection dir) +{ + dma_addr_t addr; + DMADirection expected_dir; + + if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) { + expected_dir =3D DMA_DIRECTION_FROM_DEVICE; + } else { + expected_dir =3D DMA_DIRECTION_TO_DEVICE; + } + + if (dir !=3D expected_dir) { + trace_esp_pci_error_invalid_dma_direction(); + return; + } + + if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) { + qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented= \n"); + } + + addr =3D pci->dma_regs[DMA_SPA]; + if (pci->dma_regs[DMA_WBC] < len) { + len =3D pci->dma_regs[DMA_WBC]; + } + + pci_dma_rw(&pci->dev, addr, buf, len, dir); + + /* update status registers */ + pci->dma_regs[DMA_WBC] -=3D len; + pci->dma_regs[DMA_WAC] +=3D len; +} + +static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) +{ + PCIESPState *pci =3D opaque; + esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE); +} + +static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len= ) +{ + PCIESPState *pci =3D opaque; + esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE); +} + +static const MemoryRegionOps esp_pci_io_ops =3D { + .read =3D esp_pci_io_read, + .write =3D esp_pci_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void esp_pci_hard_reset(DeviceState *dev) +{ + PCIESPState *pci =3D DO_UPCAST(PCIESPState, dev.qdev, dev); + esp_hard_reset(&pci->esp); + pci->dma_regs[DMA_CMD] &=3D ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD= _INTE_P + | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MAS= K); + pci->dma_regs[DMA_WBC] &=3D ~0xffff; + pci->dma_regs[DMA_WAC] =3D 0xffffffff; + pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT + | DMA_STAT_DONE | DMA_STAT_ABORT + | DMA_STAT_ERROR); + pci->dma_regs[DMA_WMAC] =3D 0xfffffffd; +} + +static const VMStateDescription vmstate_esp_pci_scsi =3D { + .name =3D "pciespscsi", + .version_id =3D 0, + .minimum_version_id =3D 0, + .minimum_version_id_old =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PCIESPState), + VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint3= 2_t)), + VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState), + VMSTATE_END_OF_LIST() + } +}; + +static void esp_pci_command_complete(SCSIRequest *req, uint32_t status, + size_t resid) +{ + ESPState *s =3D req->hba_private; + PCIESPState *pci =3D container_of(s, PCIESPState, esp); + + esp_command_complete(req, status, resid); + pci->dma_regs[DMA_WBC] =3D 0; + pci->dma_regs[DMA_STAT] |=3D DMA_STAT_DONE; +} + +static const struct SCSIBusInfo esp_pci_scsi_info =3D { + .tcq =3D false, + .max_target =3D ESP_MAX_DEVS, + .max_lun =3D 7, + + .transfer_data =3D esp_transfer_data, + .complete =3D esp_pci_command_complete, + .cancel =3D esp_request_cancelled, +}; + +static int esp_pci_scsi_init(PCIDevice *dev) +{ + PCIESPState *pci =3D DO_UPCAST(PCIESPState, dev, dev); + ESPState *s =3D &pci->esp; + uint8_t *pci_conf; + + pci_conf =3D pci->dev.config; + + /* Interrupt pin A */ + pci_conf[PCI_INTERRUPT_PIN] =3D 0x01; + + s->dma_memory_read =3D esp_pci_dma_memory_read; + s->dma_memory_write =3D esp_pci_dma_memory_write; + s->dma_opaque =3D pci; + s->chip_id =3D TCHI_AM53C974; + memory_region_init_io(&pci->io, &esp_pci_io_ops, pci, "esp-io", 0x80= ); + + pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); + s->irq =3D pci->dev.irq[0]; + + scsi_bus_new(&s->bus, &dev->qdev, &esp_pci_scsi_info); + if (!dev->qdev.hotplugged) { + return scsi_bus_legacy_handle_cmdline(&s->bus); + } + return 0; +} + +static void esp_pci_scsi_uninit(PCIDevice *d) +{ + PCIESPState *pci =3D DO_UPCAST(PCIESPState, dev, d); + + memory_region_destroy(&pci->io); +} + +static void esp_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->init =3D esp_pci_scsi_init; + k->exit =3D esp_pci_scsi_uninit; + k->vendor_id =3D PCI_VENDOR_ID_AMD; + k->device_id =3D PCI_DEVICE_ID_AMD_SCSI; + k->revision =3D 0x10; + k->class_id =3D PCI_CLASS_STORAGE_SCSI; + dc->desc =3D "AMD Am53c974 PCscsi-PCI SCSI adapter"; + dc->reset =3D esp_pci_hard_reset; + dc->vmsd =3D &vmstate_esp_pci_scsi; +} + +static const TypeInfo esp_pci_info =3D { + .name =3D "am53c974", + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PCIESPState), + .class_init =3D esp_pci_class_init, +}; + +static void esp_pci_register_types(void) +{ + type_register_static(&esp_pci_info); +} + +type_init(esp_pci_register_types) diff --git a/hw/esp.c b/hw/esp.c index 60c2221..52c46e6 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -24,7 +24,6 @@ */ =20 #include "sysbus.h" -#include "pci.h" #include "esp.h" #include "trace.h" #include "qemu-log.h" @@ -714,370 +713,9 @@ static const TypeInfo sysbus_esp_info =3D { .class_init =3D sysbus_esp_class_init, }; =20 -#define DMA_CMD 0x0 -#define DMA_STC 0x1 -#define DMA_SPA 0x2 -#define DMA_WBC 0x3 -#define DMA_WAC 0x4 -#define DMA_STAT 0x5 -#define DMA_SMDLA 0x6 -#define DMA_WMAC 0x7 - -#define DMA_CMD_MASK 0x03 -#define DMA_CMD_DIAG 0x04 -#define DMA_CMD_MDL 0x10 -#define DMA_CMD_INTE_P 0x20 -#define DMA_CMD_INTE_D 0x40 -#define DMA_CMD_DIR 0x80 - -#define DMA_STAT_PWDN 0x01 -#define DMA_STAT_ERROR 0x02 -#define DMA_STAT_ABORT 0x04 -#define DMA_STAT_DONE 0x08 -#define DMA_STAT_SCSIINT 0x10 -#define DMA_STAT_BCMBLT 0x20 - -#define SBAC_STATUS 0x1000 - -typedef struct PCIESPState { - PCIDevice dev; - MemoryRegion io; - uint32_t dma_regs[8]; - uint32_t sbac; - ESPState esp; -} PCIESPState; - -static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) -{ - trace_esp_pci_dma_idle(val); - esp_dma_enable(&pci->esp, 0, 0); -} - -static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) -{ - trace_esp_pci_dma_blast(val); - qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n"); -} - -static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) -{ - trace_esp_pci_dma_abort(val); - if (pci->esp.current_req) { - scsi_req_cancel(pci->esp.current_req); - } -} - -static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) -{ - trace_esp_pci_dma_start(val); - - pci->dma_regs[DMA_WBC] =3D pci->dma_regs[DMA_STC]; - pci->dma_regs[DMA_WAC] =3D pci->dma_regs[DMA_SPA]; - pci->dma_regs[DMA_WMAC] =3D pci->dma_regs[DMA_SMDLA]; - - pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT - | DMA_STAT_DONE | DMA_STAT_ABORT - | DMA_STAT_ERROR | DMA_STAT_PWDN); - - esp_dma_enable(&pci->esp, 0, 1); -} - -static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t= val) -{ - trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val); - switch (saddr) { - case DMA_CMD: - pci->dma_regs[saddr] =3D val; - switch (val & DMA_CMD_MASK) { - case 0x0: /* IDLE */ - esp_pci_handle_idle(pci, val); - break; - case 0x1: /* BLAST */ - esp_pci_handle_blast(pci, val); - break; - case 0x2: /* ABORT */ - esp_pci_handle_abort(pci, val); - break; - case 0x3: /* START */ - esp_pci_handle_start(pci, val); - break; - default: /* can't happen */ - abort(); - } - break; - case DMA_STC: - case DMA_SPA: - case DMA_SMDLA: - pci->dma_regs[saddr] =3D val; - break; - case DMA_STAT: - if (!(pci->sbac & SBAC_STATUS)) { - /* clear some bits on write */ - uint32_t mask =3D DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT= _DONE; - pci->dma_regs[DMA_STAT] &=3D ~(val & mask); - } - break; - default: - trace_esp_pci_error_invalid_write_dma(val, saddr); - return; - } -} - -static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) -{ - uint32_t val; - - val =3D pci->dma_regs[saddr]; - if (saddr =3D=3D DMA_STAT) { - if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { - val |=3D DMA_STAT_SCSIINT; - } - if (pci->sbac & SBAC_STATUS) { - pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_ERROR | DMA_STAT_ABO= RT | - DMA_STAT_DONE); - } - } - - trace_esp_pci_dma_read(saddr, val); - return val; -} - -static void esp_pci_io_write(void *opaque, target_phys_addr_t addr, - uint64_t val, unsigned int size) -{ - PCIESPState *pci =3D opaque; - - if (size < 4 || addr & 3) { - /* need to upgrade request: we only support 4-bytes accesses */ - uint32_t current =3D 0, mask; - int shift; - - if (addr < 0x40) { - current =3D pci->esp.wregs[addr >> 2]; - } else if (addr < 0x60) { - current =3D pci->dma_regs[(addr - 0x40) >> 2]; - } else if (addr < 0x74) { - current =3D pci->sbac; - } - - shift =3D (4 - size) * 8; - mask =3D (~(uint32_t)0 << shift) >> shift; - - shift =3D ((4 - (addr & 3)) & 3) * 8; - val <<=3D shift; - val |=3D current & ~(mask << shift); - addr &=3D ~3; - size =3D 4; - } - - if (addr < 0x40) { - /* SCSI core reg */ - esp_reg_write(&pci->esp, addr >> 2, val); - } else if (addr < 0x60) { - /* PCI DMA CCB */ - esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); - } else if (addr =3D=3D 0x70) { - /* DMA SCSI Bus and control */ - trace_esp_pci_sbac_write(pci->sbac, val); - pci->sbac =3D val; - } else { - trace_esp_pci_error_invalid_write((int)addr); - } -} - -static uint64_t esp_pci_io_read(void *opaque, target_phys_addr_t addr, - unsigned int size) -{ - PCIESPState *pci =3D opaque; - uint32_t ret; - - if (addr < 0x40) { - /* SCSI core reg */ - ret =3D esp_reg_read(&pci->esp, addr >> 2); - } else if (addr < 0x60) { - /* PCI DMA CCB */ - ret =3D esp_pci_dma_read(pci, (addr - 0x40) >> 2); - } else if (addr =3D=3D 0x70) { - /* DMA SCSI Bus and control */ - trace_esp_pci_sbac_read(pci->sbac); - ret =3D pci->sbac; - } else { - /* Invalid region */ - trace_esp_pci_error_invalid_read((int)addr); - ret =3D 0; - } - - /* give only requested data */ - ret >>=3D (addr & 3) * 8; - ret &=3D ~(~(uint64_t)0 << (8 * size)); - - return ret; -} - -static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int le= n, - DMADirection dir) -{ - dma_addr_t addr; - DMADirection expected_dir; - - if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) { - expected_dir =3D DMA_DIRECTION_FROM_DEVICE; - } else { - expected_dir =3D DMA_DIRECTION_TO_DEVICE; - } - - if (dir !=3D expected_dir) { - trace_esp_pci_error_invalid_dma_direction(); - return; - } - - if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) { - qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented= \n"); - } - - addr =3D pci->dma_regs[DMA_SPA]; - if (pci->dma_regs[DMA_WBC] < len) { - len =3D pci->dma_regs[DMA_WBC]; - } - - pci_dma_rw(&pci->dev, addr, buf, len, dir); - - /* update status registers */ - pci->dma_regs[DMA_WBC] -=3D len; - pci->dma_regs[DMA_WAC] +=3D len; -} - -static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) -{ - PCIESPState *pci =3D opaque; - esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE); -} - -static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len= ) -{ - PCIESPState *pci =3D opaque; - esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE); -} - -static const MemoryRegionOps esp_pci_io_ops =3D { - .read =3D esp_pci_io_read, - .write =3D esp_pci_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 4, - }, -}; - -static void esp_pci_hard_reset(DeviceState *dev) -{ - PCIESPState *pci =3D DO_UPCAST(PCIESPState, dev.qdev, dev); - esp_hard_reset(&pci->esp); - pci->dma_regs[DMA_CMD] &=3D ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD= _INTE_P - | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MAS= K); - pci->dma_regs[DMA_WBC] &=3D ~0xffff; - pci->dma_regs[DMA_WAC] =3D 0xffffffff; - pci->dma_regs[DMA_STAT] &=3D ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT - | DMA_STAT_DONE | DMA_STAT_ABORT - | DMA_STAT_ERROR); - pci->dma_regs[DMA_WMAC] =3D 0xfffffffd; -} - -static const VMStateDescription vmstate_esp_pci_scsi =3D { - .name =3D "pciespscsi", - .version_id =3D 0, - .minimum_version_id =3D 0, - .minimum_version_id_old =3D 0, - .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PCIESPState), - VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint3= 2_t)), - VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState), - VMSTATE_END_OF_LIST() - } -}; - -static void esp_pci_command_complete(SCSIRequest *req, uint32_t status, - size_t resid) -{ - ESPState *s =3D req->hba_private; - PCIESPState *pci =3D container_of(s, PCIESPState, esp); - - esp_command_complete(req, status, resid); - pci->dma_regs[DMA_WBC] =3D 0; - pci->dma_regs[DMA_STAT] |=3D DMA_STAT_DONE; -} - -static const struct SCSIBusInfo esp_pci_scsi_info =3D { - .tcq =3D false, - .max_target =3D ESP_MAX_DEVS, - .max_lun =3D 7, - - .transfer_data =3D esp_transfer_data, - .complete =3D esp_pci_command_complete, - .cancel =3D esp_request_cancelled, -}; - -static int esp_pci_scsi_init(PCIDevice *dev) -{ - PCIESPState *pci =3D DO_UPCAST(PCIESPState, dev, dev); - ESPState *s =3D &pci->esp; - uint8_t *pci_conf; - - pci_conf =3D pci->dev.config; - - /* Interrupt pin A */ - pci_conf[PCI_INTERRUPT_PIN] =3D 0x01; - - s->dma_memory_read =3D esp_pci_dma_memory_read; - s->dma_memory_write =3D esp_pci_dma_memory_write; - s->dma_opaque =3D pci; - s->chip_id =3D TCHI_AM53C974; - memory_region_init_io(&pci->io, &esp_pci_io_ops, pci, "esp-io", 0x80= ); - - pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); - s->irq =3D pci->dev.irq[0]; - - scsi_bus_new(&s->bus, &dev->qdev, &esp_pci_scsi_info); - if (!dev->qdev.hotplugged) { - return scsi_bus_legacy_handle_cmdline(&s->bus); - } - return 0; -} - -static void esp_pci_scsi_uninit(PCIDevice *d) -{ - PCIESPState *pci =3D DO_UPCAST(PCIESPState, dev, d); - - memory_region_destroy(&pci->io); -} - -static void esp_pci_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); - - k->init =3D esp_pci_scsi_init; - k->exit =3D esp_pci_scsi_uninit; - k->vendor_id =3D PCI_VENDOR_ID_AMD; - k->device_id =3D PCI_DEVICE_ID_AMD_SCSI; - k->revision =3D 0x10; - k->class_id =3D PCI_CLASS_STORAGE_SCSI; - dc->desc =3D "AMD Am53c974 PCscsi-PCI SCSI adapter"; - dc->reset =3D esp_pci_hard_reset; - dc->vmsd =3D &vmstate_esp_pci_scsi; -} - -static const TypeInfo esp_pci_info =3D { - .name =3D "am53c974", - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIESPState), - .class_init =3D esp_pci_class_init, -}; - static void esp_register_types(void) { type_register_static(&sysbus_esp_info); - type_register_static(&esp_pci_info); } =20 type_init(esp_register_types) --=20 1.7.10.4