From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzfYp-00021E-Lh for qemu-devel@nongnu.org; Thu, 09 Aug 2012 23:06:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SzfYl-00033V-4V for qemu-devel@nongnu.org; Thu, 09 Aug 2012 23:06:51 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:48073) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzfYk-0002y9-UT for qemu-devel@nongnu.org; Thu, 09 Aug 2012 23:06:47 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so1815681pbb.4 for ; Thu, 09 Aug 2012 20:06:46 -0700 (PDT) From: Jia Liu Date: Fri, 10 Aug 2012 11:05:32 +0800 Message-Id: <1344567942-11666-4-git-send-email-proljc@gmail.com> In-Reply-To: <1344567942-11666-1-git-send-email-proljc@gmail.com> References: <1344567942-11666-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH v5 03/13] target-mips-ase-dsp: Add branch instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu --- target-mips/translate.c | 52 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c2c7090..42238a8 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -332,6 +332,14 @@ enum { OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, }; +/* MIPS DSP REGIMM opcodes */ +enum { + OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, +#if defined(TARGET_MIPS64) + OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -2758,6 +2766,24 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, } btgt = ctx->pc + insn_bytes + offset; break; + case OPC_BPOSGE32: + tcg_gen_mov_tl(t0, cpu_dspctrl); +#if defined(TARGET_MIPS64) + tcg_gen_andi_tl(t0, t0, 0x7F); +#else + tcg_gen_andi_tl(t0, t0, 0x3F); +#endif + bcond_compute = 1; + btgt = ctx->pc + insn_bytes + offset; + break; +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_mov_tl(t0, cpu_dspctrl); + tcg_gen_andi_tl(t0, t0, 0x7F); + bcond_compute = 1; + btgt = ctx->pc + insn_bytes + offset; + break; +#endif case OPC_J: case OPC_JAL: case OPC_JALX: @@ -2946,6 +2972,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; + case OPC_BPOSGE32: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); + MIPS_DEBUG("bposge32 %s, " TARGET_FMT_lx, t0, btgt); + goto not_likely; +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); + MIPS_DEBUG("bposge64 %s, " TARGET_FMT_lx, t0, btgt); + goto not_likely; +#endif case OPC_BLTZALS: case OPC_BLTZAL: ctx->hflags |= (opc == OPC_BLTZALS @@ -11182,10 +11218,6 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, (ctx->opcode >> 18) & 0x7, imm << 1); *is_branch = 1; break; - case BPOSGE64: - case BPOSGE32: - /* MIPS DSP: not implemented */ - /* Fall through */ default: MIPS_INVAL("pool32i"); generate_exception(ctx, EXCP_RI); @@ -12094,6 +12126,18 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, ISA_MIPS32R2); /* Treat as NOP. */ break; + case OPC_BPOSGE32: /* MIPS DSP branch */ + check_insn(env, ctx, ASE_DSP); + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); + *is_branch = 1; + break; +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + check_insn(env, ctx, ASE_DSP); + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); + *is_branch = 1; + break; +#endif default: /* Invalid */ MIPS_INVAL("regimm"); generate_exception(ctx, EXCP_RI); -- 1.7.9.5