From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzfYx-0002Mp-40 for qemu-devel@nongnu.org; Thu, 09 Aug 2012 23:07:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SzfYu-000351-OG for qemu-devel@nongnu.org; Thu, 09 Aug 2012 23:06:58 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:48073) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzfYu-0002y9-HO for qemu-devel@nongnu.org; Thu, 09 Aug 2012 23:06:56 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so1815681pbb.4 for ; Thu, 09 Aug 2012 20:06:56 -0700 (PDT) From: Jia Liu Date: Fri, 10 Aug 2012 11:05:33 +0800 Message-Id: <1344567942-11666-5-git-send-email-proljc@gmail.com> In-Reply-To: <1344567942-11666-1-git-send-email-proljc@gmail.com> References: <1344567942-11666-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH v5 04/13] target-mips-ase-dsp: Add load instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu --- target-mips/translate.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 42238a8..febb838 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -313,6 +313,9 @@ enum { OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, + + /* MIPS DSP Load */ + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, }; /* BSHFL opcodes */ @@ -340,6 +343,17 @@ enum { #endif }; +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +/* MIPS DSP Load */ +enum { + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, +#if defined(TARGET_MIPS64) + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12084,6 +12098,61 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_LX_DSP: + op2 = MASK_LX(ctx->opcode); + switch (op2) { + case OPC_LBUX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_lbu(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } + case OPC_LHX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_lh(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } + case OPC_LWX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_lw(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } +#if defined(TARGET_MIPS64) + case OPC_LDX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_ld(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } +#endif + default: /* Invalid */ + MIPS_INVAL("MASK LX"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: -- 1.7.9.5