From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59276) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3VSf-0004ae-EH for qemu-devel@nongnu.org; Mon, 20 Aug 2012 13:08:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T3VSe-0005nc-6h for qemu-devel@nongnu.org; Mon, 20 Aug 2012 13:08:21 -0400 Received: from cantor2.suse.de ([195.135.220.15]:55376 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3VSd-0005n1-T8 for qemu-devel@nongnu.org; Mon, 20 Aug 2012 13:08:20 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 20 Aug 2012 19:07:57 +0200 Message-Id: <1345482489-5789-3-git-send-email-afaerber@suse.de> In-Reply-To: <1345482489-5789-1-git-send-email-afaerber@suse.de> References: <1345482489-5789-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH for-1.2 v7 02/14] alpha_typhoon: QOM'ify Typhoon PCI host bridge List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , anthony@codemonkey.ws, mst@redhat.com Introduce type constant and cast macro. Don't access DeviceState or PCIHostState indirectly through parent fields. Signed-off-by: Andreas F=C3=A4rber Acked-by: Michael S. Tsirkin --- hw/alpha_typhoon.c | 20 +++++++++++++------- 1 files changed, 13 insertions(+), 7 deletions(-) diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index cc63737..10e588a 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -15,6 +15,8 @@ #include "exec-memory.h" =20 =20 +#define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost" + typedef struct TyphoonCchip { MemoryRegion region; uint64_t misc; @@ -40,8 +42,12 @@ typedef struct TyphoonPchip { TyphoonWindow win[4]; } TyphoonPchip; =20 +#define TYPHOON_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE) + typedef struct TyphoonState { PCIHostState host; + TyphoonCchip cchip; TyphoonPchip pchip; MemoryRegion dchip_region; @@ -700,16 +706,16 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **= isa_bus, MemoryRegion *addr_space =3D get_system_memory(); MemoryRegion *addr_space_io =3D get_system_io(); DeviceState *dev; - PCIHostState *p; TyphoonState *s; + PCIHostState *phb; PCIBus *b; int i; =20 - dev =3D qdev_create(NULL, "typhoon-pcihost"); + dev =3D qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE); qdev_init_nofail(dev); =20 - p =3D FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); - s =3D container_of(p, TyphoonState, host); + s =3D TYPHOON_PCI_HOST_BRIDGE(dev); + phb =3D FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(dev)); =20 /* Remember the CPUs so that we can deliver interrupts to them. */ for (i =3D 0; i < 4; i++) { @@ -763,10 +769,10 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **= isa_bus, memory_region_add_subregion(addr_space, 0x801fc000000ULL, &s->pchip.reg_io); =20 - b =3D pci_register_bus(&s->host.busdev.qdev, "pci", + b =3D pci_register_bus(dev, "pci", typhoon_set_irq, sys_map_irq, s, &s->pchip.reg_mem, addr_space_io, 0, 64); - s->host.bus =3D b; + phb->bus =3D b; =20 /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. = */ memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b, @@ -818,7 +824,7 @@ static void typhoon_pcihost_class_init(ObjectClass *k= lass, void *data) } =20 static const TypeInfo typhoon_pcihost_info =3D { - .name =3D "typhoon-pcihost", + .name =3D TYPE_TYPHOON_PCI_HOST_BRIDGE, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(TyphoonState), .class_init =3D typhoon_pcihost_class_init, --=20 1.7.7