From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3bbQ-00049g-Qi for qemu-devel@nongnu.org; Mon, 20 Aug 2012 19:41:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T3bbP-0001Hy-Ep for qemu-devel@nongnu.org; Mon, 20 Aug 2012 19:41:48 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:47906) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3bbP-0001Hs-8d for qemu-devel@nongnu.org; Mon, 20 Aug 2012 19:41:47 -0400 From: Meador Inge Date: Mon, 20 Aug 2012 18:41:42 -0500 Message-ID: <1345506102-8444-1-git-send-email-meadori@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH] target-mips: Enable access to required RDHWR hardware registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net While running in the usermode emulator all of the MIPS32r2 *required* RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Signed-off-by: Meador Inge --- target-mips/translate.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 47daf85..849e75d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12768,8 +12768,11 @@ void cpu_state_reset(CPUMIPSState *env) #if defined(CONFIG_USER_ONLY) env->hflags = MIPS_HFLAG_UM; - /* Enable access to the SYNCI_Step register. */ - env->CP0_HWREna |= (1 << 1); + if (env->insn_flags & ISA_MIPS32R2) { + /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR + hardware registers. */ + env->CP0_HWREna |= 0x0000000F; + } if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->hflags |= MIPS_HFLAG_FPU; } -- 1.7.7.6