From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58151) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3sIp-0006S2-3j for qemu-devel@nongnu.org; Tue, 21 Aug 2012 13:31:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T3sIn-0002Xy-VG for qemu-devel@nongnu.org; Tue, 21 Aug 2012 13:31:43 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:48601) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3sIn-0002Xt-PN for qemu-devel@nongnu.org; Tue, 21 Aug 2012 13:31:41 -0400 From: Meador Inge Date: Tue, 21 Aug 2012 12:31:37 -0500 Message-ID: <1345570297-31562-1-git-send-email-meadori@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH for-1.2 v2] target-mips: Enable access to required RDHWR hardware registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net While running in the usermode emulator all of the required* MIPS32r2 RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Note that these registers are still enabled when the MIPS ISA is not release 2. This is OK since the Linux kernel emulates access to them when they are not available in hardware. * There is also the ULR register which is only recommended for full release 2 compliance. Incidentally, accessing this register in the current implementation works fine without flipping its access bit. Signed-off-by: Meador Inge --- v1 -> v2: * Removed (env->insn_flags & ISA_MIPS32R2) condition per feedback from Andreas and Aurelien. target-mips/translate.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 47daf85..d643676 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12768,8 +12768,9 @@ void cpu_state_reset(CPUMIPSState *env) #if defined(CONFIG_USER_ONLY) env->hflags = MIPS_HFLAG_UM; - /* Enable access to the SYNCI_Step register. */ - env->CP0_HWREna |= (1 << 1); + /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR + hardware registers. */ + env->CP0_HWREna |= 0x0000000F; if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->hflags |= MIPS_HFLAG_FPU; } -- 1.7.7.6