From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T6LNP-0005Vn-Kc for qemu-devel@nongnu.org; Tue, 28 Aug 2012 08:58:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T6LNG-0001Gl-Vc for qemu-devel@nongnu.org; Tue, 28 Aug 2012 08:58:39 -0400 Received: from mail-gg0-f173.google.com ([209.85.161.173]:38643) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T6LNG-0001Fu-Qv for qemu-devel@nongnu.org; Tue, 28 Aug 2012 08:58:30 -0400 Received: by mail-gg0-f173.google.com with SMTP id a5so1064415ggn.4 for ; Tue, 28 Aug 2012 05:58:30 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 28 Aug 2012 14:52:17 +0200 Message-Id: <1346158339-14431-3-git-send-email-pbonzini@redhat.com> In-Reply-To: <1346158339-14431-1-git-send-email-pbonzini@redhat.com> References: <1346158339-14431-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] =?utf-8?q?=5BPATCH_for_1=2E2_2/4=5D_esp=3A_support_2?= =?utf-8?q?4-bit_DMA?= List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com SeaBIOS will issue requests for more than 64k when loading a CD-ROM image into memory. Support the TCHI register from the AMD PCscsi spec. Acked-by: Hervé Poussineau Signed-off-by: Paolo Bonzini --- hw/esp.c | 16 +++++++++++----- 1 file modificato, 11 inserzioni(+), 5 rimozioni(-) diff --git a/hw/esp.c b/hw/esp.c index 52c46e6..84a4e74 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -87,7 +87,9 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf) target = s->wregs[ESP_WBUSID] & BUSID_DID; if (s->dma) { - dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); + dmalen = s->rregs[ESP_TCLO]; + dmalen |= s->rregs[ESP_TCMID] << 8; + dmalen |= s->rregs[ESP_TCHI] << 16; s->dma_memory_read(s->dma_opaque, buf, dmalen); } else { dmalen = s->ti_size; @@ -226,6 +228,7 @@ static void esp_dma_done(ESPState *s) s->rregs[ESP_RFLAGS] = 0; s->rregs[ESP_TCLO] = 0; s->rregs[ESP_TCMID] = 0; + s->rregs[ESP_TCHI] = 0; esp_raise_irq(s); } @@ -328,7 +331,9 @@ static void handle_ti(ESPState *s) return; } - dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); + dmalen = s->rregs[ESP_TCLO]; + dmalen |= s->rregs[ESP_TCMID] << 8; + dmalen |= s->rregs[ESP_TCHI] << 16; if (dmalen==0) { dmalen=0x10000; } @@ -429,6 +434,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) switch (saddr) { case ESP_TCLO: case ESP_TCMID: + case ESP_TCHI: s->rregs[ESP_RSTAT] &= ~STAT_TC; break; case ESP_FIFO: @@ -448,6 +454,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) /* Reload DMA counter. */ s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; + s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI]; } else { s->dma = 0; } @@ -530,13 +537,12 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) case ESP_WBUSID ... ESP_WSYNO: break; case ESP_CFG1: + case ESP_CFG2: case ESP_CFG3: + case ESP_RES3: case ESP_RES4: s->rregs[saddr] = val; break; case ESP_WCCF ... ESP_WTEST: break; - case ESP_CFG2 ... ESP_RES4: - s->rregs[saddr] = val; - break; default: trace_esp_error_invalid_write(val, saddr); return; -- 1.7.11.2