From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T9iJi-0001m6-0v for qemu-devel@nongnu.org; Thu, 06 Sep 2012 16:04:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T9iJg-0000kl-3P for qemu-devel@nongnu.org; Thu, 06 Sep 2012 16:04:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34807) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T9iJf-0000kQ-RA for qemu-devel@nongnu.org; Thu, 06 Sep 2012 16:04:44 -0400 From: Eduardo Habkost Date: Thu, 6 Sep 2012 17:05:36 -0300 Message-Id: <1346961939-32338-3-git-send-email-ehabkost@redhat.com> In-Reply-To: <1346961939-32338-1-git-send-email-ehabkost@redhat.com> References: <1346961939-32338-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [PATCH 2/5] i386: kvm: use a #define for the set of alias feature bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Igor Mammedov , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Anthony Liguori Instea of using a hardcoded hex constant, define CPUID_EXT2_AMD_ALIASES as the set of CPUID[8000_0001].EDX bits that on AMD are the same as the bits of CPUID[1].EDX. Signed-off-by: Eduardo Habkost Reviewed-By: Igor Mammedov --- target-i386/cpu.h | 12 ++++++++++++ target-i386/kvm.c | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index d7ea2f9..4995084 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -409,6 +409,7 @@ #define CPUID_EXT_HYPERVISOR (1 << 31) #define CPUID_EXT2_FPU (1 << 0) +#define CPUID_EXT2_VME (1 << 1) #define CPUID_EXT2_DE (1 << 2) #define CPUID_EXT2_PSE (1 << 3) #define CPUID_EXT2_TSC (1 << 4) @@ -436,6 +437,17 @@ #define CPUID_EXT2_3DNOWEXT (1 << 30) #define CPUID_EXT2_3DNOW (1 << 31) +/* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ +#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ + CPUID_EXT2_DE | CPUID_EXT2_PSE | \ + CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ + CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ + CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ + CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ + CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ + CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ + CPUID_EXT2_MMX | CPUID_EXT2_FXSR) + #define CPUID_EXT3_LAHF_LM (1 << 0) #define CPUID_EXT3_CMP_LEG (1 << 1) #define CPUID_EXT3_SVM (1 << 2) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 294af5f..895d848 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -164,7 +164,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, * so add missing bits according to the AMD spec: */ cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); - ret |= cpuid_1_edx & 0x183f3ff; + ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; break; } break; -- 1.7.11.4