From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>, Max Filippov <jcmvbkbc@gmail.com>
Subject: [Qemu-devel] [PATCH 5/9] target-xtensa: implement LSCX and LSCI groups
Date: Sun, 9 Sep 2012 05:29:54 +0400 [thread overview]
Message-ID: <1347154198-8629-6-git-send-email-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <1347154198-8629-1-git-send-email-jcmvbkbc@gmail.com>
These are load/store instructions for FP registers with immediate or
register index and optional base post-update.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target-xtensa/translate.c | 58 +++++++++++++++++++++++++++++++++++++++++---
1 files changed, 54 insertions(+), 4 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 97c388a..d167e9d 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1825,8 +1825,33 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 8: /*LSCXp*/
- HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
- TBD();
+ switch (OP2) {
+ case 0: /*LSXf*/
+ case 1: /*LSXUf*/
+ case 4: /*SSXf*/
+ case 5: /*SSXUf*/
+ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
+ gen_window_check2(dc, RRR_S, RRR_T);
+ {
+ TCGv_i32 addr = tcg_temp_new_i32();
+ tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
+ gen_load_store_alignment(dc, 2, addr, false);
+ if (OP2 & 0x4) {
+ tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
+ } else {
+ tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
+ }
+ if (OP2 & 0x1) {
+ tcg_gen_mov_i32(cpu_R[RRR_S], addr);
+ }
+ tcg_temp_free(addr);
+ }
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
break;
case 9: /*LSC4*/
@@ -2100,8 +2125,33 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 3: /*LSCIp*/
- HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
- TBD();
+ switch (RRI8_R) {
+ case 0: /*LSIf*/
+ case 4: /*SSIf*/
+ case 8: /*LSIUf*/
+ case 12: /*SSIUf*/
+ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
+ gen_window_check1(dc, RRI8_S);
+ {
+ TCGv_i32 addr = tcg_temp_new_i32();
+ tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
+ gen_load_store_alignment(dc, 2, addr, false);
+ if (RRI8_R & 0x4) {
+ tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
+ } else {
+ tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
+ }
+ if (RRI8_R & 0x8) {
+ tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
+ }
+ tcg_temp_free(addr);
+ }
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
break;
case 4: /*MAC16d*/
--
1.7.7.6
next prev parent reply other threads:[~2012-09-09 1:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-09 1:29 [Qemu-devel] [PATCH 0/9] target-xtensa: implement FP coprocessor option Max Filippov
2012-09-09 1:29 ` [Qemu-devel] [PATCH 1/9] softfloat: make float_muladd_negate_* flags independent Max Filippov
2012-09-09 9:24 ` Aurelien Jarno
2012-09-09 1:29 ` [Qemu-devel] [PATCH 2/9] target-xtensa: handle boolean option in overlays Max Filippov
2012-09-09 1:29 ` [Qemu-devel] [PATCH 3/9] target-xtensa: specialize softfloat NaN rules Max Filippov
2012-09-09 9:31 ` Peter Maydell
2012-09-09 12:13 ` Max Filippov
2012-09-09 15:14 ` Max Filippov
2012-09-09 15:44 ` Peter Maydell
2012-09-09 1:29 ` [Qemu-devel] [PATCH 4/9] target-xtensa: add FP registers Max Filippov
2012-09-09 1:29 ` Max Filippov [this message]
2012-09-09 1:29 ` [Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic Max Filippov
2012-09-09 10:05 ` Peter Maydell
2012-09-09 12:25 ` Max Filippov
2012-09-09 12:56 ` Peter Maydell
2012-09-09 1:29 ` [Qemu-devel] [PATCH 7/9] target-xtensa: implement FP0 conversions Max Filippov
2012-09-09 11:06 ` Peter Maydell
2012-09-09 12:41 ` Max Filippov
2012-09-09 1:29 ` [Qemu-devel] [PATCH 8/9] target-xtensa: implement FP1 group Max Filippov
2012-09-09 1:29 ` [Qemu-devel] [PATCH 9/9] target-xtensa: implement coprocessor context option Max Filippov
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