From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56834) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAWN0-0004yx-Dn for qemu-devel@nongnu.org; Sat, 08 Sep 2012 21:31:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAWMy-0003rB-QM for qemu-devel@nongnu.org; Sat, 08 Sep 2012 21:31:30 -0400 Received: from mail-lb0-f173.google.com ([209.85.217.173]:53999) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAWMy-0003YP-Il for qemu-devel@nongnu.org; Sat, 08 Sep 2012 21:31:28 -0400 Received: by mail-lb0-f173.google.com with SMTP id gm13so479700lbb.4 for ; Sat, 08 Sep 2012 18:31:28 -0700 (PDT) From: Max Filippov Date: Sun, 9 Sep 2012 05:29:54 +0400 Message-Id: <1347154198-8629-6-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1347154198-8629-1-git-send-email-jcmvbkbc@gmail.com> References: <1347154198-8629-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 5/9] target-xtensa: implement LSCX and LSCI groups List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Max Filippov These are load/store instructions for FP registers with immediate or register index and optional base post-update. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 58 +++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 54 insertions(+), 4 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 97c388a..d167e9d 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1825,8 +1825,33 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 8: /*LSCXp*/ - HAS_OPTION(XTENSA_OPTION_COPROCESSOR); - TBD(); + switch (OP2) { + case 0: /*LSXf*/ + case 1: /*LSXUf*/ + case 4: /*SSXf*/ + case 5: /*SSXUf*/ + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); + gen_window_check2(dc, RRR_S, RRR_T); + { + TCGv_i32 addr = tcg_temp_new_i32(); + tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); + gen_load_store_alignment(dc, 2, addr, false); + if (OP2 & 0x4) { + tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring); + } + if (OP2 & 0x1) { + tcg_gen_mov_i32(cpu_R[RRR_S], addr); + } + tcg_temp_free(addr); + } + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 9: /*LSC4*/ @@ -2100,8 +2125,33 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 3: /*LSCIp*/ - HAS_OPTION(XTENSA_OPTION_COPROCESSOR); - TBD(); + switch (RRI8_R) { + case 0: /*LSIf*/ + case 4: /*SSIf*/ + case 8: /*LSIUf*/ + case 12: /*SSIUf*/ + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); + gen_window_check1(dc, RRI8_S); + { + TCGv_i32 addr = tcg_temp_new_i32(); + tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); + gen_load_store_alignment(dc, 2, addr, false); + if (RRI8_R & 0x4) { + tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring); + } + if (RRI8_R & 0x8) { + tcg_gen_mov_i32(cpu_R[RRI8_S], addr); + } + tcg_temp_free(addr); + } + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 4: /*MAC16d*/ -- 1.7.7.6