From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Alexander Graf <agraf@suse.de>
Subject: [Qemu-devel] [PATCH 009/126] target-s390: Split out disas_jcc
Date: Sun, 9 Sep 2012 14:04:27 -0700 [thread overview]
Message-ID: <1347224784-19472-10-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net>
Lots of duplicated code replaced with a couple of tables. We no longer
attempt to manually invert the logic operation: the comments now match
the code. In the fully general test, constant propagate (1 << (3 - cc))
into (8 >> cc).
The new function will be usable by non-branch insns as well.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-s390x/translate.c | 494 +++++++++++++++++++++--------------------------
1 file changed, 215 insertions(+), 279 deletions(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index ecd6099..996d786 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -58,6 +58,18 @@ struct DisasContext {
int is_jmp;
};
+/* Information carried about a condition to be evaluated. */
+typedef struct {
+ TCGCond cond:8;
+ bool is_64;
+ bool g1;
+ bool g2;
+ union {
+ struct { TCGv_i64 a, b; } s64;
+ struct { TCGv_i32 a, b; } s32;
+ } u;
+} DisasCompare;
+
#define DISAS_EXCP 4
static void gen_op_calc_cc(DisasContext *s);
@@ -836,357 +848,281 @@ static inline void account_noninline_branch(DisasContext *s, int cc_op)
#endif
}
-static inline void account_inline_branch(DisasContext *s)
+static inline void account_inline_branch(DisasContext *s, int cc_op)
{
#ifdef DEBUG_INLINE_BRANCHES
- inline_branch_hit[s->cc_op]++;
+ inline_branch_hit[cc_op]++;
#endif
}
-static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
+/* Table of mask values to comparison codes, given a comparison as input.
+ For a true comparison CC=3 will never be set, but we treat this
+ conservatively for possible use when CC=3 indicates overflow. */
+static const TCGCond ltgt_cond[16] = {
+ TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
+ TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
+ TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
+ TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
+ TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
+ TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
+ TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
+ TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
+};
+
+/* Table of mask values to comparison codes, given a logic op as input.
+ For such, only CC=0 and CC=1 should be possible. */
+static const TCGCond nz_cond[16] = {
+ /* | | x | x */
+ TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
+ /* | NE | x | x */
+ TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
+ /* EQ | | x | x */
+ TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
+ /* EQ | NE | x | x */
+ TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
+};
+
+/* Interpret MASK in terms of S->CC_OP, and fill in C with all the
+ details required to generate a TCG comparison. */
+static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
{
- TCGv_i32 tmp, tmp2, r;
- TCGv_i64 tmp64;
- int old_cc_op;
+ TCGCond cond;
+ enum cc_op old_cc_op = s->cc_op;
- switch (s->cc_op) {
+ if (mask == 15 || mask == 0) {
+ c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
+ c->u.s32.a = cc_op;
+ c->u.s32.b = cc_op;
+ c->g1 = c->g2 = true;
+ c->is_64 = false;
+ return;
+ }
+
+ /* Find the TCG condition for the mask + cc op. */
+ switch (old_cc_op) {
case CC_OP_LTGT0_32:
- tmp = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cc_dst);
- switch (mask) {
- case 0x8 | 0x4: /* dst <= 0 */
- tcg_gen_brcondi_i32(TCG_COND_GT, tmp, 0, skip);
- break;
- case 0x8 | 0x2: /* dst >= 0 */
- tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, skip);
- break;
- case 0x8: /* dst == 0 */
- tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
- break;
- case 0x7: /* dst != 0 */
- case 0x6: /* dst != 0 */
- tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
- break;
- case 0x4: /* dst < 0 */
- tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, skip);
- break;
- case 0x2: /* dst > 0 */
- tcg_gen_brcondi_i32(TCG_COND_LE, tmp, 0, skip);
- break;
- default:
- tcg_temp_free_i32(tmp);
- goto do_dynamic;
- }
- account_inline_branch(s);
- tcg_temp_free_i32(tmp);
- break;
case CC_OP_LTGT0_64:
- switch (mask) {
- case 0x8 | 0x4: /* dst <= 0 */
- tcg_gen_brcondi_i64(TCG_COND_GT, cc_dst, 0, skip);
- break;
- case 0x8 | 0x2: /* dst >= 0 */
- tcg_gen_brcondi_i64(TCG_COND_LT, cc_dst, 0, skip);
- break;
- case 0x8: /* dst == 0 */
- tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
- break;
- case 0x7: /* dst != 0 */
- case 0x6: /* dst != 0 */
- tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
- break;
- case 0x4: /* dst < 0 */
- tcg_gen_brcondi_i64(TCG_COND_GE, cc_dst, 0, skip);
- break;
- case 0x2: /* dst > 0 */
- tcg_gen_brcondi_i64(TCG_COND_LE, cc_dst, 0, skip);
- break;
- default:
- goto do_dynamic;
- }
- account_inline_branch(s);
- break;
case CC_OP_LTGT_32:
- tmp = tcg_temp_new_i32();
- tmp2 = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cc_src);
- tcg_gen_trunc_i64_i32(tmp2, cc_dst);
- switch (mask) {
- case 0x8 | 0x4: /* src <= dst */
- tcg_gen_brcond_i32(TCG_COND_GT, tmp, tmp2, skip);
- break;
- case 0x8 | 0x2: /* src >= dst */
- tcg_gen_brcond_i32(TCG_COND_LT, tmp, tmp2, skip);
- break;
- case 0x8: /* src == dst */
- tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
- break;
- case 0x7: /* src != dst */
- case 0x6: /* src != dst */
- tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
- break;
- case 0x4: /* src < dst */
- tcg_gen_brcond_i32(TCG_COND_GE, tmp, tmp2, skip);
- break;
- case 0x2: /* src > dst */
- tcg_gen_brcond_i32(TCG_COND_LE, tmp, tmp2, skip);
- break;
- default:
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- goto do_dynamic;
- }
- account_inline_branch(s);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- break;
case CC_OP_LTGT_64:
- switch (mask) {
- case 0x8 | 0x4: /* src <= dst */
- tcg_gen_brcond_i64(TCG_COND_GT, cc_src, cc_dst, skip);
- break;
- case 0x8 | 0x2: /* src >= dst */
- tcg_gen_brcond_i64(TCG_COND_LT, cc_src, cc_dst, skip);
- break;
- case 0x8: /* src == dst */
- tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
- break;
- case 0x7: /* src != dst */
- case 0x6: /* src != dst */
- tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
- break;
- case 0x4: /* src < dst */
- tcg_gen_brcond_i64(TCG_COND_GE, cc_src, cc_dst, skip);
- break;
- case 0x2: /* src > dst */
- tcg_gen_brcond_i64(TCG_COND_LE, cc_src, cc_dst, skip);
- break;
- default:
+ cond = ltgt_cond[mask];
+ if (cond == TCG_COND_NEVER) {
goto do_dynamic;
}
- account_inline_branch(s);
+ account_inline_branch(s, old_cc_op);
break;
+
case CC_OP_LTUGTU_32:
- tmp = tcg_temp_new_i32();
- tmp2 = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cc_src);
- tcg_gen_trunc_i64_i32(tmp2, cc_dst);
- switch (mask) {
- case 0x8 | 0x4: /* src <= dst */
- tcg_gen_brcond_i32(TCG_COND_GTU, tmp, tmp2, skip);
- break;
- case 0x8 | 0x2: /* src >= dst */
- tcg_gen_brcond_i32(TCG_COND_LTU, tmp, tmp2, skip);
- break;
- case 0x8: /* src == dst */
- tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
- break;
- case 0x7: /* src != dst */
- case 0x6: /* src != dst */
- tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
- break;
- case 0x4: /* src < dst */
- tcg_gen_brcond_i32(TCG_COND_GEU, tmp, tmp2, skip);
- break;
- case 0x2: /* src > dst */
- tcg_gen_brcond_i32(TCG_COND_LEU, tmp, tmp2, skip);
- break;
- default:
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- goto do_dynamic;
- }
- account_inline_branch(s);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- break;
case CC_OP_LTUGTU_64:
- switch (mask) {
- case 0x8 | 0x4: /* src <= dst */
- tcg_gen_brcond_i64(TCG_COND_GTU, cc_src, cc_dst, skip);
- break;
- case 0x8 | 0x2: /* src >= dst */
- tcg_gen_brcond_i64(TCG_COND_LTU, cc_src, cc_dst, skip);
- break;
- case 0x8: /* src == dst */
- tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
- break;
- case 0x7: /* src != dst */
- case 0x6: /* src != dst */
- tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
- break;
- case 0x4: /* src < dst */
- tcg_gen_brcond_i64(TCG_COND_GEU, cc_src, cc_dst, skip);
- break;
- case 0x2: /* src > dst */
- tcg_gen_brcond_i64(TCG_COND_LEU, cc_src, cc_dst, skip);
- break;
- default:
+ cond = tcg_unsigned_cond(ltgt_cond[mask]);
+ if (cond == TCG_COND_NEVER) {
goto do_dynamic;
}
- account_inline_branch(s);
+ account_inline_branch(s, old_cc_op);
break;
+
case CC_OP_NZ:
- switch (mask) {
- /* dst == 0 || dst != 0 */
- case 0x8 | 0x4:
- case 0x8 | 0x4 | 0x2:
- case 0x8 | 0x4 | 0x2 | 0x1:
- case 0x8 | 0x4 | 0x1:
- break;
- /* dst == 0 */
- case 0x8:
- case 0x8 | 0x2:
- case 0x8 | 0x2 | 0x1:
- case 0x8 | 0x1:
- tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
- break;
- /* dst != 0 */
- case 0x4:
- case 0x4 | 0x2:
- case 0x4 | 0x2 | 0x1:
- case 0x4 | 0x1:
- tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
- break;
- default:
+ cond = nz_cond[mask];
+ if (cond == TCG_COND_NEVER) {
goto do_dynamic;
}
- account_inline_branch(s);
+ account_inline_branch(s, old_cc_op);
break;
- case CC_OP_TM_32:
- tmp = tcg_temp_new_i32();
- tmp2 = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cc_src);
- tcg_gen_trunc_i64_i32(tmp2, cc_dst);
- tcg_gen_and_i32(tmp, tmp, tmp2);
- switch (mask) {
- case 0x8: /* val & mask == 0 */
- tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
- break;
- case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
- tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
- break;
- default:
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- goto do_dynamic;
- }
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- account_inline_branch(s);
- break;
+ case CC_OP_TM_32:
case CC_OP_TM_64:
- tmp64 = tcg_temp_new_i64();
-
- tcg_gen_and_i64(tmp64, cc_src, cc_dst);
switch (mask) {
- case 0x8: /* val & mask == 0 */
- tcg_gen_brcondi_i64(TCG_COND_NE, tmp64, 0, skip);
+ case 8:
+ cond = TCG_COND_EQ;
break;
- case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
- tcg_gen_brcondi_i64(TCG_COND_EQ, tmp64, 0, skip);
+ case 4 | 2 | 1:
+ cond = TCG_COND_NE;
break;
default:
- tcg_temp_free_i64(tmp64);
goto do_dynamic;
}
- tcg_temp_free_i64(tmp64);
- account_inline_branch(s);
+ account_inline_branch(s, old_cc_op);
break;
+
case CC_OP_ICM:
switch (mask) {
- case 0x8: /* val == 0 */
- tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
+ case 8:
+ cond = TCG_COND_EQ;
break;
- case 0x4 | 0x2 | 0x1: /* val != 0 */
- case 0x4 | 0x2: /* val != 0 */
- tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
+ case 4 | 2 | 1:
+ case 4 | 2:
+ cond = TCG_COND_NE;
break;
default:
goto do_dynamic;
}
- account_inline_branch(s);
+ account_inline_branch(s, old_cc_op);
break;
- case CC_OP_STATIC:
- old_cc_op = s->cc_op;
- goto do_dynamic_nocccalc;
- case CC_OP_DYNAMIC:
+
default:
-do_dynamic:
- old_cc_op = s->cc_op;
- /* calculate cc value */
+ do_dynamic:
+ /* Calculate cc value. */
gen_op_calc_cc(s);
+ /* FALLTHRU */
-do_dynamic_nocccalc:
- /* jump based on cc */
+ case CC_OP_STATIC:
+ /* Jump based on CC. We'll load up the real cond below;
+ the assignment here merely avoids a compiler warning. */
account_noninline_branch(s, old_cc_op);
+ old_cc_op = CC_OP_STATIC;
+ cond = TCG_COND_NEVER;
+ break;
+ }
+
+ /* Load up the arguments of the comparison. */
+ c->is_64 = true;
+ c->g1 = c->g2 = false;
+ switch (old_cc_op) {
+ case CC_OP_LTGT0_32:
+ c->is_64 = false;
+ c->u.s32.a = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
+ c->u.s32.b = tcg_const_i32(0);
+ break;
+ case CC_OP_LTGT_32:
+ case CC_OP_LTUGTU_32:
+ c->is_64 = false;
+ c->u.s32.a = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
+ c->u.s32.b = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
+ break;
+
+ case CC_OP_LTGT0_64:
+ case CC_OP_NZ:
+ case CC_OP_ICM:
+ c->u.s64.a = cc_dst;
+ c->u.s64.b = tcg_const_i64(0);
+ c->g1 = true;
+ break;
+ case CC_OP_LTGT_64:
+ case CC_OP_LTUGTU_64:
+ c->u.s64.a = cc_src;
+ c->u.s64.b = cc_dst;
+ c->g1 = c->g2 = true;
+ break;
+
+ case CC_OP_TM_32:
+ case CC_OP_TM_64:
+ c->u.s64.a = tcg_temp_new_i64();
+ c->u.s64.b = tcg_const_i64(0);
+ tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
+ break;
+ case CC_OP_STATIC:
+ c->is_64 = false;
+ c->u.s32.a = cc_op;
+ c->g1 = true;
switch (mask) {
- case 0x8 | 0x4 | 0x2 | 0x1:
- /* always true */
- break;
case 0x8 | 0x4 | 0x2: /* cc != 3 */
- tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 3, skip);
+ cond = TCG_COND_NE;
+ c->u.s32.b = tcg_const_i32(3);
break;
case 0x8 | 0x4 | 0x1: /* cc != 2 */
- tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 2, skip);
+ cond = TCG_COND_NE;
+ c->u.s32.b = tcg_const_i32(2);
break;
case 0x8 | 0x2 | 0x1: /* cc != 1 */
- tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 1, skip);
+ cond = TCG_COND_NE;
+ c->u.s32.b = tcg_const_i32(1);
break;
- case 0x8 | 0x2: /* cc == 0 || cc == 2 */
- tmp = tcg_temp_new_i32();
- tcg_gen_andi_i32(tmp, cc_op, 1);
- tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
- tcg_temp_free_i32(tmp);
+ case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
+ cond = TCG_COND_EQ;
+ c->g1 = false;
+ c->u.s32.a = tcg_temp_new_i32();
+ c->u.s32.b = tcg_const_i32(0);
+ tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
break;
case 0x8 | 0x4: /* cc < 2 */
- tcg_gen_brcondi_i32(TCG_COND_GEU, cc_op, 2, skip);
+ cond = TCG_COND_LTU;
+ c->u.s32.b = tcg_const_i32(2);
break;
case 0x8: /* cc == 0 */
- tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 0, skip);
+ cond = TCG_COND_EQ;
+ c->u.s32.b = tcg_const_i32(0);
break;
case 0x4 | 0x2 | 0x1: /* cc != 0 */
- tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 0, skip);
+ cond = TCG_COND_NE;
+ c->u.s32.b = tcg_const_i32(0);
break;
- case 0x4 | 0x1: /* cc == 1 || cc == 3 */
- tmp = tcg_temp_new_i32();
- tcg_gen_andi_i32(tmp, cc_op, 1);
- tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
- tcg_temp_free_i32(tmp);
+ case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
+ cond = TCG_COND_NE;
+ c->g1 = false;
+ c->u.s32.a = tcg_temp_new_i32();
+ c->u.s32.b = tcg_const_i32(0);
+ tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
break;
case 0x4: /* cc == 1 */
- tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 1, skip);
+ cond = TCG_COND_EQ;
+ c->u.s32.b = tcg_const_i32(1);
break;
case 0x2 | 0x1: /* cc > 1 */
- tcg_gen_brcondi_i32(TCG_COND_LEU, cc_op, 1, skip);
+ cond = TCG_COND_GTU;
+ c->u.s32.b = tcg_const_i32(1);
break;
case 0x2: /* cc == 2 */
- tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 2, skip);
+ cond = TCG_COND_EQ;
+ c->u.s32.b = tcg_const_i32(2);
break;
case 0x1: /* cc == 3 */
- tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 3, skip);
+ cond = TCG_COND_EQ;
+ c->u.s32.b = tcg_const_i32(3);
break;
- default: /* cc is masked by something else */
- tmp = tcg_const_i32(3);
- /* 3 - cc */
- tcg_gen_sub_i32(tmp, tmp, cc_op);
- tmp2 = tcg_const_i32(1);
- /* 1 << (3 - cc) */
- tcg_gen_shl_i32(tmp2, tmp2, tmp);
- r = tcg_const_i32(mask);
- /* mask & (1 << (3 - cc)) */
- tcg_gen_and_i32(r, r, tmp2);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
-
- tcg_gen_brcondi_i32(TCG_COND_EQ, r, 0, skip);
- tcg_temp_free_i32(r);
+ default:
+ /* CC is masked by something else: (8 >> cc) & mask. */
+ cond = TCG_COND_NE;
+ c->g1 = false;
+ c->u.s32.a = tcg_const_i32(8);
+ c->u.s32.b = tcg_const_i32(0);
+ tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
+ tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
break;
}
break;
+
+ default:
+ abort();
}
+ c->cond = cond;
+}
+
+static void free_compare(DisasCompare *c)
+{
+ if (!c->g1) {
+ if (c->is_64) {
+ tcg_temp_free_i64(c->u.s64.a);
+ } else {
+ tcg_temp_free_i32(c->u.s32.a);
+ }
+ }
+ if (!c->g2) {
+ if (c->is_64) {
+ tcg_temp_free_i64(c->u.s64.b);
+ } else {
+ tcg_temp_free_i32(c->u.s32.b);
+ }
+ }
+}
+
+static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
+{
+ DisasCompare c;
+ TCGCond cond;
+
+ disas_jcc(s, &c, mask);
+ cond = tcg_invert_cond(c.cond);
+
+ if (c.is_64) {
+ tcg_gen_brcond_i64(cond, c.u.s64.a, c.u.s64.b, skip);
+ } else {
+ tcg_gen_brcond_i32(cond, c.u.s32.a, c.u.s32.b, skip);
+ }
+
+ free_compare(&c);
}
static void gen_bcr(DisasContext *s, uint32_t mask, TCGv_i64 target,
--
1.7.11.4
next prev parent reply other threads:[~2012-09-09 21:06 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-09 21:04 [Qemu-devel] [PATCH 000/126] Rewrite s390x translator Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 001/126] tcg: Add TCGV_IS_UNUSED_* Richard Henderson
2012-09-10 14:16 ` Aurelien Jarno
2012-09-09 21:04 ` [Qemu-devel] [PATCH 002/126] tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS Richard Henderson
2012-09-10 14:17 ` Aurelien Jarno
2012-09-09 21:04 ` [Qemu-devel] [PATCH 003/126] target-s390: Disassemble more z10 and z196 opcodes Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 004/126] target-s390: Fix disassembly of cpsdr Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 005/126] target-s390: Fix gdbstub Richard Henderson
2012-09-12 13:25 ` Alexander Graf
2012-09-12 15:11 ` Richard Henderson
2012-09-12 15:54 ` Alexander Graf
2012-09-12 16:15 ` Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 006/126] target-s390: Add missing temp_free in gen_op_calc_cc Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 007/126] target-s390: Use TCG registers for FPR Richard Henderson
2012-09-10 14:34 ` Aurelien Jarno
2012-09-10 14:45 ` Richard Henderson
2012-09-10 14:52 ` Aurelien Jarno
2012-09-09 21:04 ` [Qemu-devel] [PATCH 008/126] target-s390: Add format based disassassmbly infrastructure Richard Henderson
2012-09-09 21:04 ` Richard Henderson [this message]
2012-09-09 21:04 ` [Qemu-devel] [PATCH 010/126] target-s390: Reorg exception handling Richard Henderson
2012-09-18 20:18 ` Alexander Graf
2012-09-19 0:14 ` Richard Henderson
2012-09-19 11:07 ` Alexander Graf
2012-09-19 11:29 ` Peter Maydell
2012-09-19 11:34 ` Alexander Graf
2012-09-19 13:02 ` Alexander Graf
2012-09-19 14:34 ` Richard Henderson
2012-09-19 14:40 ` Alexander Graf
2012-09-09 21:04 ` [Qemu-devel] [PATCH 011/126] target-s390: Convert ADD HALFWORD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 012/126] target-s390: Implement SUBTRACT HALFWORD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 013/126] target-s390: Implement ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 014/126] target-s390: Convert MULTIPLY Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 015/126] target-s390: Convert AND, OR, XOR Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 016/126] target-s390: Convert COMPARE, COMPARE LOGICAL Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 017/126] target-s390: Convert LOAD, LOAD LOGICAL Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 018/126] target-s390: Convert LOAD ADDRESS Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 019/126] target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 020/126] target-s390: Convert LOAD AND TEST Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 021/126] target-s390: Convert LOAD LOGICAL IMMEDIATE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 022/126] target-s390: Convert LOAD COMPLIMENT, POSITIVE, NEGATIVE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 023/126] target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 024/126] target-s390: Convert STORE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 025/126] target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 026/126] target-s390: Convert BRANCH AND SAVE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 027/126] target-s390: Convert BRANCH ON CONDITION Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 028/126] target-s390: Convert BRANCH ON COUNT Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 029/126] target-s390: Convert DIVIDE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 030/126] target-s390: Send signals for divide Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 031/126] target-s390: Convert TEST UNDER MASK Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 032/126] target-s390: Convert SET ADDRESSING MODE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 033/126] target-s390: Convert SUPERVISOR CALL Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 034/126] target-s390: Convert MOVE LONG Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 035/126] target-s390: Convert FP LOAD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 036/126] target-s390: Convert INSERT CHARACTER Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 037/126] target-s390: Cleanup cc computation helpers Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 038/126] target-s390: Convert INSERT CHARACTERS UNDER MASK Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 039/126] target-s390: Convert EXECUTE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 040/126] target-s390: Convert FP STORE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 041/126] target-s390: Convert CONVERT TO DECIMAL Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 042/126] target-s390: Convert SET SYSTEM MASK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 043/126] target-s390: Convert LOAD PSW Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 044/126] target-s390: Convert DIAGNOSE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 045/126] target-s390: Convert SHIFT, ROTATE SINGLE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 046/126] target-s390: Convert SHIFT DOUBLE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 047/126] target-s390: Convert LOAD, STORE MULTIPLE Richard Henderson
2012-09-18 20:49 ` Alexander Graf
2012-09-19 0:15 ` Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 048/126] target-s390: Convert MOVE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 049/126] target-s390: Convert NI, XI, OI Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 050/126] target-s390: Convert STNSM, STOSM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 051/126] target-s390: Convert LAM, STAM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 052/126] target-s390: Convert CLCLE, MVCLE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 053/126] target-s390: Convert MVC Richard Henderson
2012-09-18 20:52 ` Alexander Graf
2012-09-09 21:05 ` [Qemu-devel] [PATCH 054/126] target-s390: Convert NC, XC, OC, TR, UNPK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 055/126] target-s390: Convert CLC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 056/126] target-s390: Convert MVCP, MVCS Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 057/126] target-s390: Convert LRA Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 058/126] target-s390: Convert SIGP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 059/126] target-s390: Convert EFPC, STFPC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 060/126] target-s390: Convert LCTL, STCTL Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 061/126] target-s390: Convert COMPARE AND SWAP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 062/126] target-s390: Convert CLM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 063/126] target-s390: Convert STCM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 064/126] target-s390: Convert TPROT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 065/126] target-s390: Convert LOAD CONTROL, part 2 Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 066/126] target-s390: Convert LOAD REVERSED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 067/126] target-s390: Convert STORE REVERSED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 068/126] target-s390: Convert LLGT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 069/126] target-s390: Convert FP ADD, COMPARE, LOAD TEST/ROUND/LENGTHENED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 070/126] target-s390: Convert FP SUBTRACT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 071/126] target-s390: Convert FP DIVIDE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 072/126] target-s390: Convert FP MULTIPLY Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 073/126] target-s390: Convert MULTIPLY AND ADD, SUBTRACT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 074/126] target-s390: Convert TEST DATA CLASS Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 075/126] target-s390: Convert FP LOAD COMPLIMENT, NEGATIVE, POSITIVE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 076/126] target-s390: Convert FP SQUARE ROOT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 077/126] target-s390: Convert LOAD ZERO Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 078/126] target-s390: Convert CONVERT TO FIXED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 079/126] target-s390: Convert CONVERT FROM FIXED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 080/126] target-s390: Convert FLOGR Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 081/126] target-s390: Convert LFPC, SFPC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 082/126] target-s390: Convert IPM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 083/126] target-s390: Convert CKSM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 084/126] target-s390: Convert EAR, SAR Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 085/126] target-s390: Convert MVPG Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 086/126] target-s390: Convert CLST, MVST Richard Henderson
2012-09-11 19:11 ` Blue Swirl
2012-09-11 21:09 ` Richard Henderson
2012-09-18 21:04 ` Alexander Graf
2012-09-09 21:05 ` [Qemu-devel] [PATCH 087/126] target-s390: Convert SRST Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 088/126] target-s390: Convert STIDP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 089/126] target-s390: Convert SCK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 090/126] target-s390: Convert STCK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 091/126] target-s390: Convert SCKC, STCKC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 092/126] target-s390: Convert SPT, STPT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 093/126] target-s390: Convert SPKA Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 094/126] target-s390: Convert PTLB Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 095/126] target-s390: Convert SPX, STPX Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 096/126] target-s390: Convert STAP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 097/126] target-s390: Convert IPTE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 098/126] target-s390: Convert ISKE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 099/126] target-s390: Convert SSKE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 100/126] target-s390: Convert RRBE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 101/126] target-s390: Convert subchannel instructions Richard Henderson
2012-09-18 21:08 ` [Qemu-devel] [PATCH 000/126] Rewrite s390x translator Alexander Graf
2012-09-18 21:09 ` Alexander Graf
2012-09-19 0:32 ` Richard Henderson
2012-09-19 11:04 ` Alexander Graf
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