From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Alexander Graf <agraf@suse.de>
Subject: [Qemu-devel] [PATCH 003/126] target-s390: Disassemble more z10 and z196 opcodes
Date: Sun, 9 Sep 2012 14:04:21 -0700 [thread overview]
Message-ID: <1347224784-19472-4-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net>
Also fix disassembly for COMPARE AND BRANCH. The table must be
sorted by primary opcode, and several were out of place.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
s390-dis.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 151 insertions(+), 18 deletions(-)
diff --git a/s390-dis.c b/s390-dis.c
index 8abcdf0..bbdd239 100644
--- a/s390-dis.c
+++ b/s390-dis.c
@@ -589,6 +589,16 @@ static const struct s390_operand s390_operands[] =
{ 4, 32, S390_OPERAND_CCODE },
#define I8_32 46 /* 8 bit signed value starting at 32 */
{ 8, 32, S390_OPERAND_SIGNED },
+#define U8_24 47 /* 8 bit unsigned value starting at 24 */
+ { 8, 24, 0 },
+#define U8_32 48 /* 8 bit unsigned value starting at 32 */
+ { 8, 32, 0 },
+#define I16_32 49
+ { 16, 32, S390_OPERAND_SIGNED },
+#define M4_16 50 /* 4-bit condition-code starting at 12 */
+ { 4, 16, S390_OPERAND_CCODE },
+#define I8_16 51
+ { 8, 16, S390_OPERAND_SIGNED },
/* QEMU-END */
};
@@ -801,11 +811,35 @@ static const struct s390_operand s390_operands[] =
#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
/* QEMU-ADD: */
-#define INSTR_RIE_MRRP 6, { M4_32,R_8,R_12,J16_16,0,0 } /* e.g. crj */
+#define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
#define MASK_RIE_MRRP { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
-#define INSTR_RIE_MRIP 6, { M4_12,R_8,I8_32,J16_16,0,0 } /* e.g. cij */
+#define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
#define MASK_RIE_MRIP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+
+#define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
+#define MASK_RIE_RRIII { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
+#define MASK_RIE_MRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define INSTR_RIE_MRU 6, { M4_32, R_8, U16_16, 0, 0, 0 } /* e.g. clfit */
+#define MASK_RIE_MRU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
+#define MASK_RIE_RRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+
+#define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 }
+#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+
+#define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 }
+#define MASK_SIL_DRI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+
+#define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 }
+#define MASK_SRY_MRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+
+#define INSTR_RRF_MRR 6, { M4_16, R_24, R_28, 0, 0, 0 }
+#define MASK_RRF_MRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+
+#define INSTR_SIY_DRI 6, { D20_20, B_16, I8_16, 0, 0, 0 }
+#define MASK_SIY_DRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
/* QEMU-END */
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
@@ -926,6 +960,30 @@ static const struct s390_opcode s390_opcodes[] =
{ "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
{ "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
{ "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
+/* QEMU-ADD: */
+ { "crj", OP48(0xec0000000076LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
+ { "cgrj", OP48(0xec0000000064LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
+ { "clrj", OP48(0xec0000000077LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
+ { "clgrj", OP48(0xec0000000065LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
+ { "cij", OP48(0xec000000007eLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
+ { "cgij", OP48(0xec000000007cLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
+ { "clij", OP48(0xec000000007fLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
+ { "clgij", OP48(0xec000000007dLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
+ { "risbg", OP48(0xec0000000055LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
+ { "risbhg", OP48(0xec000000005dLL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
+ { "risblg", OP48(0xec0000000051LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
+ { "rnsbg", OP48(0xec0000000054LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
+ { "rosbg", OP48(0xec0000000056LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
+ { "rxsbg", OP48(0xec0000000057LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
+ { "cit", OP48(0xec0000000072LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
+ { "cgit", OP48(0xec0000000070LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
+ { "clfit", OP48(0xec0000000073LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
+ { "clgit", OP48(0xec0000000071LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
+ { "ahik", OP48(0xec00000000d8LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
+ { "aghik", OP48(0xec00000000d9LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
+ { "alhsik", OP48(0xec00000000daLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
+ { "alghsik", OP48(0xec00000000dbLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
+/* QEMU-END */
{ "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0},
{ "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
{ "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
@@ -985,6 +1043,20 @@ static const struct s390_opcode s390_opcodes[] =
{ "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
{ "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
{ "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
+/* QEMU-ADD: */
+ { "loc", OP48(0xeb00000000f2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
+ { "locg", OP48(0xeb00000000e2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
+ { "stoc", OP48(0xeb00000000f3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
+ { "stocg", OP48(0xeb00000000e3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
+ { "srak", OP48(0xeb00000000dcLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
+ { "slak", OP48(0xeb00000000ddLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
+ { "srlk", OP48(0xeb00000000deLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
+ { "sllk", OP48(0xeb00000000dfLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
+ { "asi", OP48(0xeb000000006aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
+ { "alsi", OP48(0xeb000000006eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
+ { "agsi", OP48(0xeb000000007aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
+ { "algsi", OP48(0xeb000000007eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
+/* QEMU-END */
{ "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
{ "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0},
{ "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
@@ -993,6 +1065,17 @@ static const struct s390_opcode s390_opcodes[] =
{ "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
{ "strag", OP48(0xe50000000002LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2},
{ "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
+/* QEMU-ADD: */
+ { "mvhhi", OP16(0xe544LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "mvghi", OP16(0xe548LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "mvhi", OP16(0xe54cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "chhsi", OP16(0xe554LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "clhhsi", OP16(0xe555LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "cghsi", OP16(0xe558LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "clghsi", OP16(0xe559LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "chsi", OP16(0xe55cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+ { "clfhsi", OP16(0xe55dLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
+/* QEMU-END */
{ "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
{ "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
{ "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
@@ -1116,6 +1199,9 @@ static const struct s390_opcode s390_opcodes[] =
{ "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
{ "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
{ "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
+/* QEMU-ADD: */
+ { "pfd", OP48(0xe30000000036LL), MASK_RXY_URRD, INSTR_RXY_URRD, 3, 6},
+/* QEMU-END */
{ "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
{ "pku", OP8(0xe1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
{ "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
@@ -1135,6 +1221,32 @@ static const struct s390_opcode s390_opcodes[] =
{ "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
{ "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
{ "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4},
+/* QEMU-ADD: */
+ { "exrl", OP16(0xc600ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "pfdrl", OP16(0xc602ll), MASK_RIL_UP, INSTR_RIL_UP, 3, 6},
+ { "cghrl", OP16(0xc604ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "chrl", OP16(0xc605ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "clghrl", OP16(0xc606ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "clhrl", OP16(0xc607ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "cgrl", OP16(0xc608ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "clgrl", OP16(0xc60all), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "cgfrl", OP16(0xc60cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "crl", OP16(0xc60dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "clgfrl", OP16(0xc60ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "clrl", OP16(0xc60fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+
+ { "llhrl", OP16(0xc400ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "lghrl", OP16(0xc404ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "lhrl", OP16(0xc405ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "llghrl", OP16(0xc406ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "sthrl", OP16(0xc407ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "lgrl", OP16(0xc408ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "stgrl", OP16(0xc40bll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "lgfrl", OP16(0xc40cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "lrl", OP16(0xc40dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "llgfrl", OP16(0xc40ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+ { "strl", OP16(0xc40fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
+/* QEMU-END */
{ "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
{ "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
{ "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
@@ -1265,6 +1377,29 @@ static const struct s390_opcode s390_opcodes[] =
{ "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
{ "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
{ "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
+/* QEMU-ADD: */
+ { "crt", OP16(0xb972LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
+ { "cgrt", OP16(0xb960LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
+ { "clrt", OP16(0xb973LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
+ { "clgrt", OP16(0xb961LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
+ { "locr", OP16(0xb9f2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
+ { "locgr", OP16(0xb9e2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
+ { "popcnt", OP16(0xb9e1LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 6},
+ { "ngrk", OP16(0xb9e4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "ogrk", OP16(0xb9e6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "xgrk", OP16(0xb9e7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "agrk", OP16(0xb9e8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "sgrk", OP16(0xb9e9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "algrk", OP16(0xb9eaLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "slgrk", OP16(0xb9ebLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "nrk", OP16(0xb9f4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "ork", OP16(0xb9f6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "xrk", OP16(0xb9f7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "ark", OP16(0xb9f8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "srk", OP16(0xb9f9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "alrk", OP16(0xb9faLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+ { "slrk", OP16(0xb9fbLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
+/* QEMU-END */
{ "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
{ "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
{ "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
@@ -1426,6 +1561,20 @@ static const struct s390_opcode s390_opcodes[] =
{ "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
{ "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
{ "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
+/* QEMU-ADD: */
+ { "clfebr", OP16(0xb39cLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "clfdbr", OP16(0xb39dLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "clfxbr", OP16(0xb39eLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "clgebr", OP16(0xb3acLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "clgdbr", OP16(0xb3adLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "clgxbr", OP16(0xb3aeLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "celfbr", OP16(0xb390LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "cdlfbr", OP16(0xb391LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "cxlfbr", OP16(0xb392LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "celgbr", OP16(0xb3a0LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "cdlgbr", OP16(0xb3a1LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+ { "cxlgbr", OP16(0xb3a2LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
+/* QEMU-END */
{ "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0},
{ "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5},
{ "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5},
@@ -1774,22 +1923,6 @@ static const struct s390_opcode s390_opcodes[] =
{ "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0},
{ "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0},
{ "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0},
-
-/* QEMU-ADD: */
- { "crj", OP48(0xec0000000076LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
- { "cgrj", OP48(0xec0000000064LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
- { "clrj", OP48(0xec0000000077LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
- { "clgrj", OP48(0xec0000000065LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
-
- { "cij", OP48(0xec000000007eLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
- { "cgij", OP48(0xec000000007cLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
- { "clij", OP48(0xec000000007fLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
- { "clgij", OP48(0xec000000007dLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
-
- { "lrl", OP16(0xc40dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
- { "lgrl", OP16(0xc408ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
- { "lgfrl", OP16(0xc40cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
-/* QEMU-END */
};
static const int s390_num_opcodes =
--
1.7.11.4
next prev parent reply other threads:[~2012-09-09 21:06 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-09 21:04 [Qemu-devel] [PATCH 000/126] Rewrite s390x translator Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 001/126] tcg: Add TCGV_IS_UNUSED_* Richard Henderson
2012-09-10 14:16 ` Aurelien Jarno
2012-09-09 21:04 ` [Qemu-devel] [PATCH 002/126] tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS Richard Henderson
2012-09-10 14:17 ` Aurelien Jarno
2012-09-09 21:04 ` Richard Henderson [this message]
2012-09-09 21:04 ` [Qemu-devel] [PATCH 004/126] target-s390: Fix disassembly of cpsdr Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 005/126] target-s390: Fix gdbstub Richard Henderson
2012-09-12 13:25 ` Alexander Graf
2012-09-12 15:11 ` Richard Henderson
2012-09-12 15:54 ` Alexander Graf
2012-09-12 16:15 ` Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 006/126] target-s390: Add missing temp_free in gen_op_calc_cc Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 007/126] target-s390: Use TCG registers for FPR Richard Henderson
2012-09-10 14:34 ` Aurelien Jarno
2012-09-10 14:45 ` Richard Henderson
2012-09-10 14:52 ` Aurelien Jarno
2012-09-09 21:04 ` [Qemu-devel] [PATCH 008/126] target-s390: Add format based disassassmbly infrastructure Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 009/126] target-s390: Split out disas_jcc Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 010/126] target-s390: Reorg exception handling Richard Henderson
2012-09-18 20:18 ` Alexander Graf
2012-09-19 0:14 ` Richard Henderson
2012-09-19 11:07 ` Alexander Graf
2012-09-19 11:29 ` Peter Maydell
2012-09-19 11:34 ` Alexander Graf
2012-09-19 13:02 ` Alexander Graf
2012-09-19 14:34 ` Richard Henderson
2012-09-19 14:40 ` Alexander Graf
2012-09-09 21:04 ` [Qemu-devel] [PATCH 011/126] target-s390: Convert ADD HALFWORD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 012/126] target-s390: Implement SUBTRACT HALFWORD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 013/126] target-s390: Implement ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 014/126] target-s390: Convert MULTIPLY Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 015/126] target-s390: Convert AND, OR, XOR Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 016/126] target-s390: Convert COMPARE, COMPARE LOGICAL Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 017/126] target-s390: Convert LOAD, LOAD LOGICAL Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 018/126] target-s390: Convert LOAD ADDRESS Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 019/126] target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 020/126] target-s390: Convert LOAD AND TEST Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 021/126] target-s390: Convert LOAD LOGICAL IMMEDIATE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 022/126] target-s390: Convert LOAD COMPLIMENT, POSITIVE, NEGATIVE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 023/126] target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 024/126] target-s390: Convert STORE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 025/126] target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 026/126] target-s390: Convert BRANCH AND SAVE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 027/126] target-s390: Convert BRANCH ON CONDITION Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 028/126] target-s390: Convert BRANCH ON COUNT Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 029/126] target-s390: Convert DIVIDE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 030/126] target-s390: Send signals for divide Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 031/126] target-s390: Convert TEST UNDER MASK Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 032/126] target-s390: Convert SET ADDRESSING MODE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 033/126] target-s390: Convert SUPERVISOR CALL Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 034/126] target-s390: Convert MOVE LONG Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 035/126] target-s390: Convert FP LOAD Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 036/126] target-s390: Convert INSERT CHARACTER Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 037/126] target-s390: Cleanup cc computation helpers Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 038/126] target-s390: Convert INSERT CHARACTERS UNDER MASK Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 039/126] target-s390: Convert EXECUTE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 040/126] target-s390: Convert FP STORE Richard Henderson
2012-09-09 21:04 ` [Qemu-devel] [PATCH 041/126] target-s390: Convert CONVERT TO DECIMAL Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 042/126] target-s390: Convert SET SYSTEM MASK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 043/126] target-s390: Convert LOAD PSW Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 044/126] target-s390: Convert DIAGNOSE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 045/126] target-s390: Convert SHIFT, ROTATE SINGLE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 046/126] target-s390: Convert SHIFT DOUBLE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 047/126] target-s390: Convert LOAD, STORE MULTIPLE Richard Henderson
2012-09-18 20:49 ` Alexander Graf
2012-09-19 0:15 ` Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 048/126] target-s390: Convert MOVE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 049/126] target-s390: Convert NI, XI, OI Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 050/126] target-s390: Convert STNSM, STOSM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 051/126] target-s390: Convert LAM, STAM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 052/126] target-s390: Convert CLCLE, MVCLE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 053/126] target-s390: Convert MVC Richard Henderson
2012-09-18 20:52 ` Alexander Graf
2012-09-09 21:05 ` [Qemu-devel] [PATCH 054/126] target-s390: Convert NC, XC, OC, TR, UNPK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 055/126] target-s390: Convert CLC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 056/126] target-s390: Convert MVCP, MVCS Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 057/126] target-s390: Convert LRA Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 058/126] target-s390: Convert SIGP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 059/126] target-s390: Convert EFPC, STFPC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 060/126] target-s390: Convert LCTL, STCTL Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 061/126] target-s390: Convert COMPARE AND SWAP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 062/126] target-s390: Convert CLM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 063/126] target-s390: Convert STCM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 064/126] target-s390: Convert TPROT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 065/126] target-s390: Convert LOAD CONTROL, part 2 Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 066/126] target-s390: Convert LOAD REVERSED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 067/126] target-s390: Convert STORE REVERSED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 068/126] target-s390: Convert LLGT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 069/126] target-s390: Convert FP ADD, COMPARE, LOAD TEST/ROUND/LENGTHENED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 070/126] target-s390: Convert FP SUBTRACT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 071/126] target-s390: Convert FP DIVIDE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 072/126] target-s390: Convert FP MULTIPLY Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 073/126] target-s390: Convert MULTIPLY AND ADD, SUBTRACT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 074/126] target-s390: Convert TEST DATA CLASS Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 075/126] target-s390: Convert FP LOAD COMPLIMENT, NEGATIVE, POSITIVE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 076/126] target-s390: Convert FP SQUARE ROOT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 077/126] target-s390: Convert LOAD ZERO Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 078/126] target-s390: Convert CONVERT TO FIXED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 079/126] target-s390: Convert CONVERT FROM FIXED Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 080/126] target-s390: Convert FLOGR Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 081/126] target-s390: Convert LFPC, SFPC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 082/126] target-s390: Convert IPM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 083/126] target-s390: Convert CKSM Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 084/126] target-s390: Convert EAR, SAR Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 085/126] target-s390: Convert MVPG Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 086/126] target-s390: Convert CLST, MVST Richard Henderson
2012-09-11 19:11 ` Blue Swirl
2012-09-11 21:09 ` Richard Henderson
2012-09-18 21:04 ` Alexander Graf
2012-09-09 21:05 ` [Qemu-devel] [PATCH 087/126] target-s390: Convert SRST Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 088/126] target-s390: Convert STIDP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 089/126] target-s390: Convert SCK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 090/126] target-s390: Convert STCK Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 091/126] target-s390: Convert SCKC, STCKC Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 092/126] target-s390: Convert SPT, STPT Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 093/126] target-s390: Convert SPKA Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 094/126] target-s390: Convert PTLB Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 095/126] target-s390: Convert SPX, STPX Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 096/126] target-s390: Convert STAP Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 097/126] target-s390: Convert IPTE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 098/126] target-s390: Convert ISKE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 099/126] target-s390: Convert SSKE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 100/126] target-s390: Convert RRBE Richard Henderson
2012-09-09 21:05 ` [Qemu-devel] [PATCH 101/126] target-s390: Convert subchannel instructions Richard Henderson
2012-09-18 21:08 ` [Qemu-devel] [PATCH 000/126] Rewrite s390x translator Alexander Graf
2012-09-18 21:09 ` Alexander Graf
2012-09-19 0:32 ` Richard Henderson
2012-09-19 11:04 ` Alexander Graf
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1347224784-19472-4-git-send-email-rth@twiddle.net \
--to=rth@twiddle.net \
--cc=agraf@suse.de \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).