* [Qemu-devel] [PATCH 01/11] target-sh4: mark a few helpers const and pure
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 02/11] target-sh4: use float32_muladd() to implement fmac Aurelien Jarno
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/helper.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 6e4f108..d498719 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -23,8 +23,8 @@ DEF_HELPER_3(macw, void, env, i32, i32)
DEF_HELPER_2(ld_fpscr, void, env, i32)
-DEF_HELPER_1(fabs_FT, f32, f32)
-DEF_HELPER_1(fabs_DT, f64, f64)
+DEF_HELPER_FLAGS_1(fabs_FT, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32)
+DEF_HELPER_FLAGS_1(fabs_DT, TCG_CALL_CONST | TCG_CALL_PURE, f64, f64)
DEF_HELPER_3(fadd_FT, f32, env, f32, f32)
DEF_HELPER_3(fadd_DT, f64, env, f64, f64)
DEF_HELPER_2(fcnvsd_FT_DT, f64, env, f32)
@@ -41,7 +41,7 @@ DEF_HELPER_2(float_DT, f64, env, i32)
DEF_HELPER_4(fmac_FT, f32, env, f32, f32, f32)
DEF_HELPER_3(fmul_FT, f32, env, f32, f32)
DEF_HELPER_3(fmul_DT, f64, env, f64, f64)
-DEF_HELPER_1(fneg_T, f32, f32)
+DEF_HELPER_FLAGS_1(fneg_T, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32)
DEF_HELPER_3(fsub_FT, f32, env, f32, f32)
DEF_HELPER_3(fsub_DT, f64, env, f64, f64)
DEF_HELPER_2(fsqrt_FT, f32, env, f32)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 02/11] target-sh4: use float32_muladd() to implement fmac
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 01/11] target-sh4: mark a few helpers const and pure Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 03/11] target-sh4: implement addc and subc using TCG Aurelien Jarno
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
There is no need to add a SH4 specific pickNaNMulAdd() to softfloat as
SH4 is always returning a default NaN.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 9b4328d..bf835fa 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -623,8 +623,7 @@ float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
{
set_float_exception_flags(0, &env->fp_status);
- t0 = float32_mul(t0, t1, &env->fp_status);
- t0 = float32_add(t0, t2, &env->fp_status);
+ t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
update_fpscr(env, GETPC());
return t0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 03/11] target-sh4: implement addc and subc using TCG
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 01/11] target-sh4: mark a few helpers const and pure Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 02/11] target-sh4: use float32_muladd() to implement fmac Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 04/11] target-sh4: implement addv and subv " Aurelien Jarno
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
Now that setcond is available, the addc and subc can easily be
implemented using TCG.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/helper.h | 2 --
target-sh4/op_helper.c | 32 --------------------------------
target-sh4/translate.c | 38 ++++++++++++++++++++++++++++++++++++--
3 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index d498719..92d6dd7 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -14,9 +14,7 @@ DEF_HELPER_1(discard_movcal_backup, void, env)
DEF_HELPER_2(ocbi, void, env, i32)
DEF_HELPER_3(addv, i32, env, i32, i32)
-DEF_HELPER_3(addc, i32, env, i32, i32)
DEF_HELPER_3(subv, i32, env, i32, i32)
-DEF_HELPER_3(subc, i32, env, i32, i32)
DEF_HELPER_3(div1, i32, env, i32, i32)
DEF_HELPER_3(macl, void, env, i32, i32)
DEF_HELPER_3(macw, void, env, i32, i32)
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index bf835fa..3ad10ba 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -177,22 +177,6 @@ void helper_ocbi(CPUSH4State *env, uint32_t address)
}
}
-uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
-{
- uint32_t tmp0, tmp1;
-
- tmp1 = arg0 + arg1;
- tmp0 = arg1;
- arg1 = tmp1 + (env->sr & 1);
- if (tmp0 > tmp1)
- env->sr |= SR_T;
- else
- env->sr &= ~SR_T;
- if (tmp1 > arg1)
- env->sr |= SR_T;
- return arg1;
-}
-
uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t dest, src, ans;
@@ -375,22 +359,6 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
}
}
-uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
-{
- uint32_t tmp0, tmp1;
-
- tmp1 = arg1 - arg0;
- tmp0 = arg1;
- arg1 = tmp1 - (env->sr & SR_T);
- if (tmp0 < tmp1)
- env->sr |= SR_T;
- else
- env->sr &= ~SR_T;
- if (tmp1 < arg1)
- env->sr |= SR_T;
- return arg1;
-}
-
uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
int32_t dest, src, ans;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d05c74c..92f9b46 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -761,7 +761,24 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300e: /* addc Rm,Rn */
- gen_helper_addc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
+ {
+ TCGv t0, t1, t2;
+ t0 = tcg_temp_new();
+ tcg_gen_andi_i32(t0, cpu_sr, SR_T);
+ t1 = tcg_temp_new();
+ tcg_gen_add_i32(t1, REG(B7_4), REG(B11_8));
+ tcg_gen_add_i32(t0, t0, t1);
+ t2 = tcg_temp_new();
+ tcg_gen_setcond_i32(TCG_COND_GTU, t2, REG(B11_8), t1);
+ tcg_gen_setcond_i32(TCG_COND_GTU, t1, t1, t0);
+ tcg_gen_or_i32(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+ tcg_temp_free(t1);
+ tcg_gen_mov_i32(REG(B11_8), t0);
+ tcg_temp_free(t0);
+ }
return;
case 0x300f: /* addv Rm,Rn */
gen_helper_addv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
@@ -1013,7 +1030,24 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300a: /* subc Rm,Rn */
- gen_helper_subc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
+ {
+ TCGv t0, t1, t2;
+ t0 = tcg_temp_new();
+ tcg_gen_andi_i32(t0, cpu_sr, SR_T);
+ t1 = tcg_temp_new();
+ tcg_gen_sub_i32(t1, REG(B11_8), REG(B7_4));
+ tcg_gen_sub_i32(t0, t1, t0);
+ t2 = tcg_temp_new();
+ tcg_gen_setcond_i32(TCG_COND_LTU, t2, REG(B11_8), t1);
+ tcg_gen_setcond_i32(TCG_COND_LTU, t1, t1, t0);
+ tcg_gen_or_i32(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+ tcg_temp_free(t1);
+ tcg_gen_mov_i32(REG(B11_8), t0);
+ tcg_temp_free(t0);
+ }
return;
case 0x300b: /* subv Rm,Rn */
gen_helper_subv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 04/11] target-sh4: implement addv and subv using TCG
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (2 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 03/11] target-sh4: implement addc and subc using TCG Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 05/11] target-sh4: optimize xtrct Aurelien Jarno
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
addv and subv helpers implementation is directly copied from the SH4
manual and looks quite complex. It is however possible to explain it
without branches, and is therefore possible to implement it with TCG.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/helper.h | 2 --
target-sh4/op_helper.c | 58 ------------------------------------------------
target-sh4/translate.c | 36 ++++++++++++++++++++++++++++--
3 files changed, 34 insertions(+), 62 deletions(-)
diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 92d6dd7..a00b7dd 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -13,8 +13,6 @@ DEF_HELPER_3(movcal, void, env, i32, i32)
DEF_HELPER_1(discard_movcal_backup, void, env)
DEF_HELPER_2(ocbi, void, env, i32)
-DEF_HELPER_3(addv, i32, env, i32, i32)
-DEF_HELPER_3(subv, i32, env, i32, i32)
DEF_HELPER_3(div1, i32, env, i32, i32)
DEF_HELPER_3(macl, void, env, i32, i32)
DEF_HELPER_3(macw, void, env, i32, i32)
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 3ad10ba..4f1f754 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -177,35 +177,6 @@ void helper_ocbi(CPUSH4State *env, uint32_t address)
}
}
-uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
-{
- uint32_t dest, src, ans;
-
- if ((int32_t) arg1 >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) arg0 >= 0)
- src = 0;
- else
- src = 1;
- src += dest;
- arg1 += arg0;
- if ((int32_t) arg1 >= 0)
- ans = 0;
- else
- ans = 1;
- ans += dest;
- if (src == 0 || src == 2) {
- if (ans == 1)
- env->sr |= SR_T;
- else
- env->sr &= ~SR_T;
- } else
- env->sr &= ~SR_T;
- return arg1;
-}
-
#define T (env->sr & SR_T)
#define Q (env->sr & SR_Q ? 1 : 0)
#define M (env->sr & SR_M ? 1 : 0)
@@ -359,35 +330,6 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
}
}
-uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
-{
- int32_t dest, src, ans;
-
- if ((int32_t) arg1 >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) arg0 >= 0)
- src = 0;
- else
- src = 1;
- src += dest;
- arg1 -= arg0;
- if ((int32_t) arg1 >= 0)
- ans = 0;
- else
- ans = 1;
- ans += dest;
- if (src == 1) {
- if (ans == 1)
- env->sr |= SR_T;
- else
- env->sr &= ~SR_T;
- } else
- env->sr &= ~SR_T;
- return arg1;
-}
-
static inline void set_t(CPUSH4State *env)
{
env->sr |= SR_T;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 92f9b46..41a1f22 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -781,7 +781,23 @@ static void _decode_opc(DisasContext * ctx)
}
return;
case 0x300f: /* addv Rm,Rn */
- gen_helper_addv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
+ {
+ TCGv t0, t1, t2;
+ t0 = tcg_temp_new();
+ tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8));
+ t1 = tcg_temp_new();
+ tcg_gen_xor_i32(t1, t0, REG(B11_8));
+ t2 = tcg_temp_new();
+ tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
+ tcg_gen_andc_i32(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_shri_i32(t1, t1, 31);
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+ tcg_temp_free(t1);
+ tcg_gen_mov_i32(REG(B7_4), t0);
+ tcg_temp_free(t0);
+ }
return;
case 0x2009: /* and Rm,Rn */
tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
@@ -1050,7 +1066,23 @@ static void _decode_opc(DisasContext * ctx)
}
return;
case 0x300b: /* subv Rm,Rn */
- gen_helper_subv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
+ {
+ TCGv t0, t1, t2;
+ t0 = tcg_temp_new();
+ tcg_gen_sub_i32(t0, REG(B11_8), REG(B7_4));
+ t1 = tcg_temp_new();
+ tcg_gen_xor_i32(t1, t0, REG(B7_4));
+ t2 = tcg_temp_new();
+ tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4));
+ tcg_gen_and_i32(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_shri_i32(t1, t1, 31);
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+ tcg_temp_free(t1);
+ tcg_gen_mov_i32(REG(B11_8), t0);
+ tcg_temp_free(t0);
+ }
return;
case 0x2008: /* tst Rm,Rn */
{
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 05/11] target-sh4: optimize xtrct
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (3 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 04/11] target-sh4: implement addv and subv " Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 06/11] target-sh4: optimize swap.w Aurelien Jarno
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
The register being 32 bit long, after a shift to the right by 16 bits,
the upper 16 bit are already cleared. There is no need to call ext16u
to clear them.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 41a1f22..92c5a1f 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -751,7 +751,6 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_shli_i32(high, REG(B7_4), 16);
low = tcg_temp_new();
tcg_gen_shri_i32(low, REG(B11_8), 16);
- tcg_gen_ext16u_i32(low, low);
tcg_gen_or_i32(REG(B11_8), high, low);
tcg_temp_free(low);
tcg_temp_free(high);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 06/11] target-sh4: optimize swap.w
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (4 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 05/11] target-sh4: optimize xtrct Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 07/11] target-sh4: remove gen_clr_t() and gen_set_t() Aurelien Jarno
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
It's possible swap the two 16-bit words of a 32-bit register using a
rotation. If the TCG target doesn't implement rotation, the replacement
code is similar to the previously implemented code.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/translate.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 92c5a1f..9ecbe47 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -732,17 +732,7 @@ static void _decode_opc(DisasContext * ctx)
}
return;
case 0x6009: /* swap.w Rm,Rn */
- {
- TCGv high, low;
- high = tcg_temp_new();
- tcg_gen_shli_i32(high, REG(B7_4), 16);
- low = tcg_temp_new();
- tcg_gen_shri_i32(low, REG(B7_4), 16);
- tcg_gen_ext16u_i32(low, low);
- tcg_gen_or_i32(REG(B11_8), high, low);
- tcg_temp_free(low);
- tcg_temp_free(high);
- }
+ tcg_gen_rotli_i32(REG(B11_8), REG(B7_4), 16);
return;
case 0x200d: /* xtrct Rm,Rn */
{
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 07/11] target-sh4: remove gen_clr_t() and gen_set_t()
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (5 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 06/11] target-sh4: optimize swap.w Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 08/11] target-sh4: rework exceptions handling Aurelien Jarno
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
gen_clr_t() and gen_set_t() have very few callers and can be remplaced
by a single line. Remove them.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/translate.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 9ecbe47..cdc4e3b 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -339,16 +339,6 @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
gen_jump(ctx);
}
-static inline void gen_set_t(void)
-{
- tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
-}
-
-static inline void gen_clr_t(void)
-{
- tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
-}
-
static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
{
TCGv t;
@@ -519,7 +509,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
return;
case 0x0008: /* clrt */
- gen_clr_t();
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
return;
case 0x0038: /* ldtlb */
CHECK_PRIVILEGED
@@ -537,7 +527,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
return;
case 0x0018: /* sett */
- gen_set_t();
+ tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
return;
case 0xfbfd: /* frchg */
tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
@@ -1660,7 +1650,7 @@ static void _decode_opc(DisasContext * ctx)
*/
if (ctx->features & SH_FEATURE_SH4A) {
int label = gen_new_label();
- gen_clr_t();
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 08/11] target-sh4: rework exceptions handling
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (6 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 07/11] target-sh4: remove gen_clr_t() and gen_set_t() Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 09/11] target-sh4: cleanup DisasContext Aurelien Jarno
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
Since commit fd4bab102 PC is restored in case of exception through code
retranslation. While it is clearly the thing to do in case it is not
not known if an helper is going to trigger an exception or not
(e.g. for load/store, FPU, etc.), it just make things slower when the
exception is already known at translation time.
Partially revert this commit and save PC in the TCG code. Set bstate to
BS_BRANCH to not generate TCG exit code. Micro-optimize the sleep
helper. Make all the exception helpers to call raise_exception and mark
it as noreturn.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/helper.h | 14 +++++++-------
target-sh4/op_helper.c | 30 +++++++++++++-----------------
target-sh4/translate.c | 18 ++++++++++++------
3 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index a00b7dd..6c1a47d 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -1,13 +1,13 @@
#include "def-helper.h"
DEF_HELPER_1(ldtlb, void, env)
-DEF_HELPER_1(raise_illegal_instruction, void, env)
-DEF_HELPER_1(raise_slot_illegal_instruction, void, env)
-DEF_HELPER_1(raise_fpu_disable, void, env)
-DEF_HELPER_1(raise_slot_fpu_disable, void, env)
-DEF_HELPER_1(debug, void, env)
-DEF_HELPER_2(sleep, void, env, i32)
-DEF_HELPER_2(trapa, void, env, i32)
+DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
+DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
+DEF_HELPER_1(raise_fpu_disable, noreturn, env)
+DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
+DEF_HELPER_1(debug, noreturn, env)
+DEF_HELPER_1(sleep, noreturn, env)
+DEF_HELPER_2(trapa, noreturn, env, i32)
DEF_HELPER_3(movcal, void, env, i32, i32)
DEF_HELPER_1(discard_movcal_backup, void, env)
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 4f1f754..60ec4cb 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -21,7 +21,8 @@
#include "cpu.h"
#include "helper.h"
-static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
+static inline void cpu_restore_state_from_retaddr(CPUSH4State *env,
+ uintptr_t retaddr)
{
TranslationBlock *tb;
@@ -77,8 +78,8 @@ void helper_ldtlb(CPUSH4State *env)
#endif
}
-static inline void raise_exception(CPUSH4State *env, int index,
- uintptr_t retaddr)
+static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
+ uintptr_t retaddr)
{
env->exception_index = index;
cpu_restore_state_from_retaddr(env, retaddr);
@@ -87,43 +88,40 @@ static inline void raise_exception(CPUSH4State *env, int index,
void helper_raise_illegal_instruction(CPUSH4State *env)
{
- raise_exception(env, 0x180, GETPC());
+ raise_exception(env, 0x180, 0);
}
void helper_raise_slot_illegal_instruction(CPUSH4State *env)
{
- raise_exception(env, 0x1a0, GETPC());
+ raise_exception(env, 0x1a0, 0);
}
void helper_raise_fpu_disable(CPUSH4State *env)
{
- raise_exception(env, 0x800, GETPC());
+ raise_exception(env, 0x800, 0);
}
void helper_raise_slot_fpu_disable(CPUSH4State *env)
{
- raise_exception(env, 0x820, GETPC());
+ raise_exception(env, 0x820, 0);
}
void helper_debug(CPUSH4State *env)
{
- env->exception_index = EXCP_DEBUG;
- cpu_loop_exit(env);
+ raise_exception(env, EXCP_DEBUG, 0);
}
-void helper_sleep(CPUSH4State *env, uint32_t next_pc)
+void helper_sleep(CPUSH4State *env)
{
env->halted = 1;
env->in_sleep = 1;
- env->exception_index = EXCP_HLT;
- env->pc = next_pc;
- cpu_loop_exit(env);
+ raise_exception(env, EXCP_HLT, 0);
}
void helper_trapa(CPUSH4State *env, uint32_t tra)
{
env->tra = tra << 2;
- raise_exception(env, 0x160, GETPC());
+ raise_exception(env, 0x160, 0);
}
void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
@@ -385,9 +383,7 @@ static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
if (cause & enable) {
- cpu_restore_state_from_retaddr(env, retaddr);
- env->exception_index = 0x120;
- cpu_loop_exit(env);
+ raise_exception(env, 0x120, retaddr);
}
}
}
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index cdc4e3b..6305db8 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -427,30 +427,33 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
#define CHECK_NOT_DELAY_SLOT \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
{ \
+ tcg_gen_movi_i32(cpu_pc, ctx->pc); \
gen_helper_raise_slot_illegal_instruction(cpu_env); \
- ctx->bstate = BS_EXCP; \
+ ctx->bstate = BS_BRANCH; \
return; \
}
#define CHECK_PRIVILEGED \
if (IS_USER(ctx)) { \
+ tcg_gen_movi_i32(cpu_pc, ctx->pc); \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
gen_helper_raise_slot_illegal_instruction(cpu_env); \
} else { \
gen_helper_raise_illegal_instruction(cpu_env); \
} \
- ctx->bstate = BS_EXCP; \
+ ctx->bstate = BS_BRANCH; \
return; \
}
#define CHECK_FPU_ENABLED \
if (ctx->flags & SR_FD) { \
+ tcg_gen_movi_i32(cpu_pc, ctx->pc); \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
gen_helper_raise_slot_fpu_disable(cpu_env); \
} else { \
gen_helper_raise_fpu_disable(cpu_env); \
} \
- ctx->bstate = BS_EXCP; \
+ ctx->bstate = BS_BRANCH; \
return; \
}
@@ -541,7 +544,8 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x001b: /* sleep */
CHECK_PRIVILEGED
- gen_helper_sleep(cpu_env, tcg_const_i32(ctx->pc + 2));
+ tcg_gen_movi_i32(cpu_pc, ctx->pc + 2);
+ gen_helper_sleep(cpu_env);
return;
}
@@ -1411,6 +1415,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv imm;
CHECK_NOT_DELAY_SLOT
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
imm = tcg_const_i32(B7_0);
gen_helper_trapa(cpu_env, imm);
tcg_temp_free(imm);
@@ -1909,12 +1914,13 @@ static void _decode_opc(DisasContext * ctx)
ctx->opcode, ctx->pc);
fflush(stderr);
#endif
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
gen_helper_raise_slot_illegal_instruction(cpu_env);
} else {
gen_helper_raise_illegal_instruction(cpu_env);
}
- ctx->bstate = BS_EXCP;
+ ctx->bstate = BS_BRANCH;
}
static void decode_opc(DisasContext * ctx)
@@ -1992,7 +1998,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
/* We have hit a breakpoint - make sure PC is up-to-date */
tcg_gen_movi_i32(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
- ctx.bstate = BS_EXCP;
+ ctx.bstate = BS_BRANCH;
break;
}
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 09/11] target-sh4: cleanup DisasContext
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (7 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 08/11] target-sh4: rework exceptions handling Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:11 ` [Qemu-devel] [PATCH 10/11] target-sh4: remove useless code Aurelien Jarno
2012-09-16 23:12 ` [Qemu-devel] [PATCH 11/11] gdbstub/sh4: fix build with USE_SOFTFLOAT_STRUCT_TYPES Aurelien Jarno
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
We should avoid accessing env at translation stage, except of course for
static values like the supported features.
Remove variables copied from env in DisasContext and use the TB flags
instead.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/translate.c | 56 ++++++++++++++++++++++--------------------------
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 6305db8..e5478cb 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -32,8 +32,6 @@
typedef struct DisasContext {
struct TranslationBlock *tb;
target_ulong pc;
- uint32_t sr;
- uint32_t fpscr;
uint16_t opcode;
uint32_t flags;
int bstate;
@@ -47,7 +45,7 @@ typedef struct DisasContext {
#if defined(CONFIG_USER_ONLY)
#define IS_USER(ctx) 1
#else
-#define IS_USER(ctx) (!(ctx->sr & SR_MD))
+#define IS_USER(ctx) (!(ctx->flags & SR_MD))
#endif
enum {
@@ -413,15 +411,15 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
#define B11_8 ((ctx->opcode >> 8) & 0xf)
#define B15_12 ((ctx->opcode >> 12) & 0xf)
-#define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
- (cpu_gregs[x + 16]) : (cpu_gregs[x]))
+#define REG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) == (SR_MD | SR_RB) \
+ ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
-#define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
+#define ALTREG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) != (SR_MD | SR_RB)\
? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
-#define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
+#define FREG(x) (ctx->flags & FPSCR_FR ? (x) ^ 0x10 : (x))
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
+#define XREG(x) (ctx->flags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
#define CHECK_NOT_DELAY_SLOT \
@@ -537,7 +535,7 @@ static void _decode_opc(DisasContext * ctx)
ctx->bstate = BS_STOP;
return;
case 0xf3fd: /* fschg */
- tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
+ tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
ctx->bstate = BS_STOP;
return;
case 0x0009: /* nop */
@@ -1080,7 +1078,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->flags & FPSCR_SZ) {
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(fp, XREG(B7_4));
gen_store_fpr64(fp, XREG(B11_8));
@@ -1091,7 +1089,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->flags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
int fr = XREG(B7_4);
tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
@@ -1104,7 +1102,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->flags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
int fr = XREG(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
@@ -1117,7 +1115,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->flags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
int fr = XREG(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
@@ -1132,7 +1130,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->flags & FPSCR_SZ) {
TCGv addr = tcg_temp_new_i32();
int fr = XREG(B7_4);
tcg_gen_subi_i32(addr, REG(B11_8), 4);
@@ -1155,7 +1153,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
- if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->flags & FPSCR_SZ) {
int fr = XREG(B11_8);
tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
tcg_gen_addi_i32(addr, addr, 4);
@@ -1171,7 +1169,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
- if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->flags & FPSCR_SZ) {
int fr = XREG(B7_4);
tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
tcg_gen_addi_i32(addr, addr, 4);
@@ -1190,7 +1188,7 @@ static void _decode_opc(DisasContext * ctx)
case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
{
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->flags & FPSCR_PR) {
TCGv_i64 fp0, fp1;
if (ctx->opcode & 0x0110)
@@ -1259,7 +1257,7 @@ static void _decode_opc(DisasContext * ctx)
case 0xf00e: /* fmac FR0,RM,Rn */
{
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->flags & FPSCR_PR) {
break; /* illegal instruction */
} else {
gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
@@ -1789,7 +1787,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->flags & FPSCR_PR) {
TCGv_i64 fp;
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
@@ -1804,7 +1802,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->flags & FPSCR_PR) {
TCGv_i64 fp;
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
@@ -1825,7 +1823,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf05d: /* fabs FRn/DRn */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->flags & FPSCR_PR) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
TCGv_i64 fp = tcg_temp_new_i64();
@@ -1839,7 +1837,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf06d: /* fsqrt FRn */
CHECK_FPU_ENABLED
- if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->flags & FPSCR_PR) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
TCGv_i64 fp = tcg_temp_new_i64();
@@ -1857,13 +1855,13 @@ static void _decode_opc(DisasContext * ctx)
break;
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
CHECK_FPU_ENABLED
- if (!(ctx->fpscr & FPSCR_PR)) {
+ if (!(ctx->flags & FPSCR_PR)) {
tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
}
return;
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
CHECK_FPU_ENABLED
- if (!(ctx->fpscr & FPSCR_PR)) {
+ if (!(ctx->flags & FPSCR_PR)) {
tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
}
return;
@@ -1887,7 +1885,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf0ed: /* fipr FVm,FVn */
CHECK_FPU_ENABLED
- if ((ctx->fpscr & FPSCR_PR) == 0) {
+ if ((ctx->flags & FPSCR_PR) == 0) {
TCGv m, n;
m = tcg_const_i32((ctx->opcode >> 8) & 3);
n = tcg_const_i32((ctx->opcode >> 10) & 3);
@@ -1900,7 +1898,7 @@ static void _decode_opc(DisasContext * ctx)
case 0xf0fd: /* ftrv XMTRX,FVn */
CHECK_FPU_ENABLED
if ((ctx->opcode & 0x0300) == 0x0100 &&
- (ctx->fpscr & FPSCR_PR) == 0) {
+ (ctx->flags & FPSCR_PR) == 0) {
TCGv n;
n = tcg_const_i32((ctx->opcode >> 10) & 3);
gen_helper_ftrv(cpu_env, n);
@@ -1974,16 +1972,14 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
ctx.pc = pc_start;
ctx.flags = (uint32_t)tb->flags;
ctx.bstate = BS_NONE;
- ctx.sr = env->sr;
- ctx.fpscr = env->fpscr;
- ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0;
+ ctx.memidx = (ctx.flags & SR_MD) == 0 ? 1 : 0;
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
ctx.singlestep_enabled = env->singlestep_enabled;
ctx.features = env->features;
- ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA);
+ ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
ii = -1;
num_insns = 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 10/11] target-sh4: remove useless code
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (8 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 09/11] target-sh4: cleanup DisasContext Aurelien Jarno
@ 2012-09-16 23:11 ` Aurelien Jarno
2012-09-16 23:12 ` [Qemu-devel] [PATCH 11/11] gdbstub/sh4: fix build with USE_SOFTFLOAT_STRUCT_TYPES Aurelien Jarno
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
Almost dead code.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-sh4/translate.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index e5478cb..0fa83ca 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -18,7 +18,6 @@
*/
#define DEBUG_DISAS
-#define SH4_DEBUG_DISAS
//#define SH4_SINGLE_STEP
#include "cpu.h"
@@ -2069,9 +2068,6 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
}
#ifdef DEBUG_DISAS
-#ifdef SH4_DEBUG_DISAS
- qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
-#endif
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
log_target_disas(pc_start, ctx.pc - pc_start, 0);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH 11/11] gdbstub/sh4: fix build with USE_SOFTFLOAT_STRUCT_TYPES
2012-09-16 23:11 [Qemu-devel] [PATCH 00/11] target-sh4: misc optimizations and cleanup Aurelien Jarno
` (9 preceding siblings ...)
2012-09-16 23:11 ` [Qemu-devel] [PATCH 10/11] target-sh4: remove useless code Aurelien Jarno
@ 2012-09-16 23:12 ` Aurelien Jarno
10 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2012-09-16 23:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
We have to use different type to access float values when
USE_SOFTFLOAT_STRUCT_TYPES is defined.
Rework SH4 version of cpu_gdb_{read,write}_register() using
a single case, and fixing the coding style. Use ldll_p() and
stfl_p() to access float values.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
gdbstub.c | 144 ++++++++++++++++++++++++++++++++++++++-----------------------
1 file changed, 90 insertions(+), 54 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 5d37dd9..a91709f 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1226,33 +1226,48 @@ static int cpu_gdb_write_register(CPUOpenRISCState *env,
static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
- if (n < 8) {
+ switch (n) {
+ case 0 ... 7:
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
GET_REGL(env->gregs[n + 16]);
} else {
GET_REGL(env->gregs[n]);
}
- } else if (n < 16) {
+ case 8 ... 15:
GET_REGL(env->gregs[n]);
- } else if (n >= 25 && n < 41) {
- GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
- } else if (n >= 43 && n < 51) {
- GET_REGL(env->gregs[n - 43]);
- } else if (n >= 51 && n < 59) {
- GET_REGL(env->gregs[n - (51 - 16)]);
- }
- switch (n) {
- case 16: GET_REGL(env->pc);
- case 17: GET_REGL(env->pr);
- case 18: GET_REGL(env->gbr);
- case 19: GET_REGL(env->vbr);
- case 20: GET_REGL(env->mach);
- case 21: GET_REGL(env->macl);
- case 22: GET_REGL(env->sr);
- case 23: GET_REGL(env->fpul);
- case 24: GET_REGL(env->fpscr);
- case 41: GET_REGL(env->ssr);
- case 42: GET_REGL(env->spc);
+ case 16:
+ GET_REGL(env->pc);
+ case 17:
+ GET_REGL(env->pr);
+ case 18:
+ GET_REGL(env->gbr);
+ case 19:
+ GET_REGL(env->vbr);
+ case 20:
+ GET_REGL(env->mach);
+ case 21:
+ GET_REGL(env->macl);
+ case 22:
+ GET_REGL(env->sr);
+ case 23:
+ GET_REGL(env->fpul);
+ case 24:
+ GET_REGL(env->fpscr);
+ case 25 ... 40:
+ if (env->fpscr & FPSCR_FR) {
+ stfl_p(mem_buf, env->fregs[n - 9]);
+ } else {
+ stfl_p(mem_buf, env->fregs[n - 25]);
+ }
+ return 4;
+ case 41:
+ GET_REGL(env->ssr);
+ case 42:
+ GET_REGL(env->spc);
+ case 43 ... 50:
+ GET_REGL(env->gregs[n - 43]);
+ case 51 ... 58:
+ GET_REGL(env->gregs[n - (51 - 16)]);
}
return 0;
@@ -1260,42 +1275,63 @@ static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
- uint32_t tmp;
-
- tmp = ldl_p(mem_buf);
-
- if (n < 8) {
+ switch (n) {
+ case 0 ... 7:
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
- env->gregs[n + 16] = tmp;
+ env->gregs[n + 16] = ldl_p(mem_buf);
} else {
- env->gregs[n] = tmp;
+ env->gregs[n] = ldl_p(mem_buf);
}
- return 4;
- } else if (n < 16) {
- env->gregs[n] = tmp;
- return 4;
- } else if (n >= 25 && n < 41) {
- env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
- return 4;
- } else if (n >= 43 && n < 51) {
- env->gregs[n - 43] = tmp;
- return 4;
- } else if (n >= 51 && n < 59) {
- env->gregs[n - (51 - 16)] = tmp;
- return 4;
- }
- switch (n) {
- case 16: env->pc = tmp; break;
- case 17: env->pr = tmp; break;
- case 18: env->gbr = tmp; break;
- case 19: env->vbr = tmp; break;
- case 20: env->mach = tmp; break;
- case 21: env->macl = tmp; break;
- case 22: env->sr = tmp; break;
- case 23: env->fpul = tmp; break;
- case 24: env->fpscr = tmp; break;
- case 41: env->ssr = tmp; break;
- case 42: env->spc = tmp; break;
+ break;
+ case 8 ... 15:
+ env->gregs[n] = ldl_p(mem_buf);
+ break;
+ case 16:
+ env->pc = ldl_p(mem_buf);
+ break;
+ case 17:
+ env->pr = ldl_p(mem_buf);
+ break;
+ case 18:
+ env->gbr = ldl_p(mem_buf);
+ break;
+ case 19:
+ env->vbr = ldl_p(mem_buf);
+ break;
+ case 20:
+ env->mach = ldl_p(mem_buf);
+ break;
+ case 21:
+ env->macl = ldl_p(mem_buf);
+ break;
+ case 22:
+ env->sr = ldl_p(mem_buf);
+ break;
+ case 23:
+ env->fpul = ldl_p(mem_buf);
+ break;
+ case 24:
+ env->fpscr = ldl_p(mem_buf);
+ break;
+ case 25 ... 40:
+ if (env->fpscr & FPSCR_FR) {
+ env->fregs[n - 9] = ldfl_p(mem_buf);
+ } else {
+ env->fregs[n - 25] = ldfl_p(mem_buf);
+ }
+ break;
+ case 41:
+ env->ssr = ldl_p(mem_buf);
+ break;
+ case 42:
+ env->spc = ldl_p(mem_buf);
+ break;
+ case 43 ... 50:
+ env->gregs[n - 43] = ldl_p(mem_buf);
+ break;
+ case 51 ... 58:
+ env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
+ break;
default: return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread