From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO0T-0000wq-QD for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDO0R-0008AO-N7 for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:05 -0400 Received: from hall.aurel32.net ([88.191.126.93]:47763) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO0R-00089m-GR for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:03 -0400 From: Aurelien Jarno Date: Mon, 17 Sep 2012 01:11:55 +0200 Message-Id: <1347837120-14422-7-git-send-email-aurelien@aurel32.net> In-Reply-To: <1347837120-14422-1-git-send-email-aurelien@aurel32.net> References: <1347837120-14422-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 06/11] target-sh4: optimize swap.w List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno It's possible swap the two 16-bit words of a 32-bit register using a rotation. If the TCG target doesn't implement rotation, the replacement code is similar to the previously implemented code. Signed-off-by: Aurelien Jarno --- target-sh4/translate.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 92c5a1f..9ecbe47 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -732,17 +732,7 @@ static void _decode_opc(DisasContext * ctx) } return; case 0x6009: /* swap.w Rm,Rn */ - { - TCGv high, low; - high = tcg_temp_new(); - tcg_gen_shli_i32(high, REG(B7_4), 16); - low = tcg_temp_new(); - tcg_gen_shri_i32(low, REG(B7_4), 16); - tcg_gen_ext16u_i32(low, low); - tcg_gen_or_i32(REG(B11_8), high, low); - tcg_temp_free(low); - tcg_temp_free(high); - } + tcg_gen_rotli_i32(REG(B11_8), REG(B7_4), 16); return; case 0x200d: /* xtrct Rm,Rn */ { -- 1.7.10.4