From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDdG7-0004Zf-2H for qemu-devel@nongnu.org; Mon, 17 Sep 2012 11:29:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDdG5-0005mL-Md for qemu-devel@nongnu.org; Mon, 17 Sep 2012 11:29:14 -0400 Received: from mail-qa0-f52.google.com ([209.85.216.52]:51587) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDdG5-0005gZ-J8 for qemu-devel@nongnu.org; Mon, 17 Sep 2012 11:29:13 -0400 Received: by mail-qa0-f52.google.com with SMTP id g14so1598216qab.4 for ; Mon, 17 Sep 2012 08:29:13 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Sep 2012 08:28:48 -0700 Message-Id: <1347895732-22212-10-git-send-email-rth@twiddle.net> In-Reply-To: <1347895732-22212-1-git-send-email-rth@twiddle.net> References: <1347895732-22212-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 09/13] tcg-sparc: Mask shift immediates to avoid illegal insns. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index e625aa3..be5c170 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, goto gen_arith; case INDEX_op_shl_i32: c = SHIFT_SLL; - goto gen_arith; + do_shift32: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c); + break; case INDEX_op_shr_i32: c = SHIFT_SRL; - goto gen_arith; + goto do_shift32; case INDEX_op_sar_i32: c = SHIFT_SRA; - goto gen_arith; + goto do_shift32; case INDEX_op_mul_i32: c = ARITH_UMUL; goto gen_arith; @@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_shl_i64: c = SHIFT_SLLX; - goto gen_arith; + do_shift64: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c); + break; case INDEX_op_shr_i64: c = SHIFT_SRLX; - goto gen_arith; + goto do_shift64; case INDEX_op_sar_i64: c = SHIFT_SRAX; - goto gen_arith; + goto do_shift64; case INDEX_op_mul_i64: c = ARITH_MULX; goto gen_arith; -- 1.7.11.4