From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 6/7] target-mips: Add accessors for the two 32-bit halves of a 64-bit FPR
Date: Mon, 17 Sep 2012 14:35:12 -0700 [thread overview]
Message-ID: <1347917713-23343-7-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1347917713-23343-1-git-send-email-rth@twiddle.net>
Not much used yet, but more users to come.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-mips/translate.c | 64 +++++++++++++++++++++++++++++--------------------
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index df92cec..57454f0 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -754,6 +754,24 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
+static void gen_load_fpr_pair(DisasContext *ctx, TCGv_i32 tl,
+ TCGv_i32 th, int reg)
+{
+ gen_load_fpr32(ctx, tl, reg);
+ gen_load_fpr32h(ctx, th, reg);
+}
+
+static void gen_store_fpr_pair(DisasContext *ctx, TCGv_i32 tl,
+ TCGv_i32 th, int reg)
+{
+ if (ctx->hflags & MIPS_HFLAG_F64) {
+ tcg_gen_concat_i32_i64(fpu_f64[reg], tl, th);
+ } else {
+ tcg_gen_mov_i32(fpu_f32[reg], tl);
+ tcg_gen_mov_i32(fpu_fh32[reg], th);
+ }
+}
+
static inline int get_fp_bit (int cc)
{
if (cc)
@@ -7671,8 +7689,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_store_fpr32h(ctx, fp0, fd);
- gen_store_fpr32(ctx, fp1, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7686,8 +7703,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32h(ctx, fp1, ft);
- gen_store_fpr32(ctx, fp1, fd);
- gen_store_fpr32h(ctx, fp0, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7701,8 +7717,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32h(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_store_fpr32(ctx, fp1, fd);
- gen_store_fpr32h(ctx, fp0, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7716,8 +7731,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32h(ctx, fp0, fs);
gen_load_fpr32h(ctx, fp1, ft);
- gen_store_fpr32(ctx, fp1, fd);
- gen_store_fpr32h(ctx, fp0, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7877,8 +7891,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
check_cp1_64bitmode(ctx);
{
TCGv t0 = tcg_temp_local_new();
- TCGv_i32 fp = tcg_temp_new_i32();
- TCGv_i32 fph = tcg_temp_new_i32();
+ TCGv_i32 fp, fph;
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -7886,28 +7899,27 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
tcg_gen_andi_tl(t0, t0, 0x7);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- gen_load_fpr32(ctx, fp, fs);
- gen_load_fpr32h(ctx, fph, fs);
- gen_store_fpr32(ctx, fp, fd);
- gen_store_fpr32h(ctx, fph, fd);
+
+ fp = tcg_temp_new_i32();
+ fph = tcg_temp_new_i32();
+ gen_load_fpr_pair(ctx, fp, fph, fs);
+ gen_store_fpr_pair(ctx, fp, fph, fd);
+ tcg_temp_free_i32(fp);
+ tcg_temp_free_i32(fph);
tcg_gen_br(l2);
+
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
tcg_temp_free(t0);
-#ifdef TARGET_WORDS_BIGENDIAN
- gen_load_fpr32(ctx, fp, fs);
- gen_load_fpr32h(ctx, fph, ft);
- gen_store_fpr32h(ctx, fp, fd);
- gen_store_fpr32(ctx, fph, fd);
-#else
- gen_load_fpr32h(ctx, fph, fs);
- gen_load_fpr32(ctx, fp, ft);
- gen_store_fpr32(ctx, fph, fd);
- gen_store_fpr32h(ctx, fp, fd);
-#endif
- gen_set_label(l2);
+
+ fp = tcg_temp_new_i32();
+ fph = tcg_temp_new_i32();
+ gen_load_fpr_pair(ctx, fp, fph, fs);
+ gen_store_fpr_pair(ctx, fph, fp, fd);
tcg_temp_free_i32(fp);
tcg_temp_free_i32(fph);
+
+ gen_set_label(l2);
}
opn = "alnv.ps";
break;
--
1.7.11.4
next prev parent reply other threads:[~2012-09-17 21:35 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-17 21:35 [Qemu-devel] [PATCH v2 0/7] target-mips improvements Richard Henderson
2012-09-17 21:35 ` [Qemu-devel] [PATCH 1/7] target-mips: Set opn in gen_ldst_multiple Richard Henderson
2012-09-18 16:38 ` Aurelien Jarno
2012-09-17 21:35 ` [Qemu-devel] [PATCH 2/7] target-mips: Fix MIPS_DEBUG Richard Henderson
2012-09-18 16:38 ` Aurelien Jarno
2012-09-17 21:35 ` [Qemu-devel] [PATCH 3/7] target-mips: Always evaluate debugging macro arguments Richard Henderson
2012-09-18 16:38 ` Aurelien Jarno
2012-09-17 21:35 ` [Qemu-devel] [PATCH 4/7] target-mips: Pass DisasContext to fpr32 load/store routines Richard Henderson
2012-09-18 16:39 ` Aurelien Jarno
2012-09-17 21:35 ` [Qemu-devel] [PATCH 5/7] target-mips: Use TCG registers for the FPU Richard Henderson
2012-09-18 16:39 ` Aurelien Jarno
2012-09-17 21:35 ` Richard Henderson [this message]
2012-09-17 21:35 ` [Qemu-devel] [PATCH 7/7] target-mips: Implement Loongson Multimedia Instructions Richard Henderson
2012-09-18 16:39 ` Aurelien Jarno
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