* [Qemu-devel] [PATCH stable] tci: Fix for AREG0 free mode
@ 2012-09-18 20:43 Stefan Weil
2012-09-27 18:49 ` Stefan Weil
2012-09-27 19:29 ` Aurelien Jarno
0 siblings, 2 replies; 3+ messages in thread
From: Stefan Weil @ 2012-09-18 20:43 UTC (permalink / raw)
To: Blue Swirl; +Cc: Stefan Weil, qemu-devel
Support for helper functions with 5 arguments was missing
in the code generator and in the interpreter.
There is no need to pass the constant TCG_AREG0 from the
code generator to the interpreter. Remove that code for
the INDEX_op_qemu_st* opcodes.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
---
This patch is also needed for stable-1.2.
Regards
Stefan Weil
tcg/tci/tcg-target.c | 10 +++++-----
tci.c | 13 +++++++++----
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
index 3f4a24b..d272a90 100644
--- a/tcg/tci/tcg-target.c
+++ b/tcg/tci/tcg-target.c
@@ -300,7 +300,7 @@ static const int tcg_target_reg_alloc_order[] = {
#endif
};
-#if MAX_OPC_PARAM_IARGS != 4
+#if MAX_OPC_PARAM_IARGS != 5
# error Fix needed, number of supported input arguments changed!
#endif
@@ -309,16 +309,18 @@ static const int tcg_target_call_iarg_regs[] = {
TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
-#if TCG_TARGET_REG_BITS == 32
- /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
#if 0 /* used for TCG_REG_CALL_STACK */
TCG_REG_R4,
#endif
TCG_REG_R5,
+#if TCG_TARGET_REG_BITS == 32
+ /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
TCG_REG_R6,
TCG_REG_R7,
#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
+ TCG_REG_R9,
+ TCG_REG_R10,
#else
# error Too few input registers available
#endif
@@ -798,7 +800,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_st8:
case INDEX_op_qemu_st16:
case INDEX_op_qemu_st32:
- tcg_out_r(s, TCG_AREG0);
tcg_out_r(s, *args++);
tcg_out_r(s, *args++);
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
@@ -809,7 +810,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
#endif
break;
case INDEX_op_qemu_st64:
- tcg_out_r(s, TCG_AREG0);
tcg_out_r(s, *args++);
#if TCG_TARGET_REG_BITS == 32
tcg_out_r(s, *args++);
diff --git a/tci.c b/tci.c
index ce8a988..a4f7b78 100644
--- a/tci.c
+++ b/tci.c
@@ -36,17 +36,19 @@
tcg_abort(); \
} while (0)
-#if MAX_OPC_PARAM_IARGS != 4
+#if MAX_OPC_PARAM_IARGS != 5
# error Fix needed, number of supported input arguments changed!
#endif
#if TCG_TARGET_REG_BITS == 32
typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
tcg_target_ulong, tcg_target_ulong,
tcg_target_ulong, tcg_target_ulong,
+ tcg_target_ulong, tcg_target_ulong,
tcg_target_ulong, tcg_target_ulong);
#else
typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong);
+ tcg_target_ulong, tcg_target_ulong,
+ tcg_target_ulong);
#endif
/* TCI can optionally use a global register variable for env. */
@@ -489,14 +491,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
tci_read_reg(TCG_REG_R5),
tci_read_reg(TCG_REG_R6),
tci_read_reg(TCG_REG_R7),
- tci_read_reg(TCG_REG_R8));
+ tci_read_reg(TCG_REG_R8),
+ tci_read_reg(TCG_REG_R9),
+ tci_read_reg(TCG_REG_R10));
tci_write_reg(TCG_REG_R0, tmp64);
tci_write_reg(TCG_REG_R1, tmp64 >> 32);
#else
tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
tci_read_reg(TCG_REG_R1),
tci_read_reg(TCG_REG_R2),
- tci_read_reg(TCG_REG_R3));
+ tci_read_reg(TCG_REG_R3),
+ tci_read_reg(TCG_REG_R5));
tci_write_reg(TCG_REG_R0, tmp64);
#endif
break;
--
1.7.10
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH stable] tci: Fix for AREG0 free mode
2012-09-18 20:43 [Qemu-devel] [PATCH stable] tci: Fix for AREG0 free mode Stefan Weil
@ 2012-09-27 18:49 ` Stefan Weil
2012-09-27 19:29 ` Aurelien Jarno
1 sibling, 0 replies; 3+ messages in thread
From: Stefan Weil @ 2012-09-27 18:49 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
Am 18.09.2012 22:43, schrieb Stefan Weil:
> Support for helper functions with 5 arguments was missing
> in the code generator and in the interpreter.
>
> There is no need to pass the constant TCG_AREG0 from the
> code generator to the interpreter. Remove that code for
> the INDEX_op_qemu_st* opcodes.
>
> Signed-off-by: Stefan Weil<sw@weilnetz.de>
> ---
>
> This patch is also needed for stable-1.2.
>
> Regards
>
> Stefan Weil
>
Ping? Maybe my mail was misleading: the patch is needed
to get a working TCI for QEMU stable-1.2 _and_ for the latest QEMU.
This is a bug fix, so I expect that a pull request is not needed.
Thanks,
Stefan
>
> tcg/tci/tcg-target.c | 10 +++++-----
> tci.c | 13 +++++++++----
> 2 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
> index 3f4a24b..d272a90 100644
> --- a/tcg/tci/tcg-target.c
> +++ b/tcg/tci/tcg-target.c
> @@ -300,7 +300,7 @@ static const int tcg_target_reg_alloc_order[] = {
> #endif
> };
>
> -#if MAX_OPC_PARAM_IARGS != 4
> +#if MAX_OPC_PARAM_IARGS != 5
> # error Fix needed, number of supported input arguments changed!
> #endif
>
> @@ -309,16 +309,18 @@ static const int tcg_target_call_iarg_regs[] = {
> TCG_REG_R1,
> TCG_REG_R2,
> TCG_REG_R3,
> -#if TCG_TARGET_REG_BITS == 32
> - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
> #if 0 /* used for TCG_REG_CALL_STACK */
> TCG_REG_R4,
> #endif
> TCG_REG_R5,
> +#if TCG_TARGET_REG_BITS == 32
> + /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
> TCG_REG_R6,
> TCG_REG_R7,
> #if TCG_TARGET_NB_REGS>= 16
> TCG_REG_R8,
> + TCG_REG_R9,
> + TCG_REG_R10,
> #else
> # error Too few input registers available
> #endif
> @@ -798,7 +800,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_qemu_st8:
> case INDEX_op_qemu_st16:
> case INDEX_op_qemu_st32:
> - tcg_out_r(s, TCG_AREG0);
> tcg_out_r(s, *args++);
> tcg_out_r(s, *args++);
> #if TARGET_LONG_BITS> TCG_TARGET_REG_BITS
> @@ -809,7 +810,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> #endif
> break;
> case INDEX_op_qemu_st64:
> - tcg_out_r(s, TCG_AREG0);
> tcg_out_r(s, *args++);
> #if TCG_TARGET_REG_BITS == 32
> tcg_out_r(s, *args++);
> diff --git a/tci.c b/tci.c
> index ce8a988..a4f7b78 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -36,17 +36,19 @@
> tcg_abort(); \
> } while (0)
>
> -#if MAX_OPC_PARAM_IARGS != 4
> +#if MAX_OPC_PARAM_IARGS != 5
> # error Fix needed, number of supported input arguments changed!
> #endif
> #if TCG_TARGET_REG_BITS == 32
> typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
> tcg_target_ulong, tcg_target_ulong,
> tcg_target_ulong, tcg_target_ulong,
> + tcg_target_ulong, tcg_target_ulong,
> tcg_target_ulong, tcg_target_ulong);
> #else
> typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
> - tcg_target_ulong, tcg_target_ulong);
> + tcg_target_ulong, tcg_target_ulong,
> + tcg_target_ulong);
> #endif
>
> /* TCI can optionally use a global register variable for env. */
> @@ -489,14 +491,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
> tci_read_reg(TCG_REG_R5),
> tci_read_reg(TCG_REG_R6),
> tci_read_reg(TCG_REG_R7),
> - tci_read_reg(TCG_REG_R8));
> + tci_read_reg(TCG_REG_R8),
> + tci_read_reg(TCG_REG_R9),
> + tci_read_reg(TCG_REG_R10));
> tci_write_reg(TCG_REG_R0, tmp64);
> tci_write_reg(TCG_REG_R1, tmp64>> 32);
> #else
> tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
> tci_read_reg(TCG_REG_R1),
> tci_read_reg(TCG_REG_R2),
> - tci_read_reg(TCG_REG_R3));
> + tci_read_reg(TCG_REG_R3),
> + tci_read_reg(TCG_REG_R5));
> tci_write_reg(TCG_REG_R0, tmp64);
> #endif
> break;
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH stable] tci: Fix for AREG0 free mode
2012-09-18 20:43 [Qemu-devel] [PATCH stable] tci: Fix for AREG0 free mode Stefan Weil
2012-09-27 18:49 ` Stefan Weil
@ 2012-09-27 19:29 ` Aurelien Jarno
1 sibling, 0 replies; 3+ messages in thread
From: Aurelien Jarno @ 2012-09-27 19:29 UTC (permalink / raw)
To: Stefan Weil; +Cc: Blue Swirl, qemu-devel
On Tue, Sep 18, 2012 at 10:43:38PM +0200, Stefan Weil wrote:
> Support for helper functions with 5 arguments was missing
> in the code generator and in the interpreter.
>
> There is no need to pass the constant TCG_AREG0 from the
> code generator to the interpreter. Remove that code for
> the INDEX_op_qemu_st* opcodes.
>
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> ---
>
> This patch is also needed for stable-1.2.
>
> Regards
>
> Stefan Weil
>
>
> tcg/tci/tcg-target.c | 10 +++++-----
> tci.c | 13 +++++++++----
> 2 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
> index 3f4a24b..d272a90 100644
> --- a/tcg/tci/tcg-target.c
> +++ b/tcg/tci/tcg-target.c
> @@ -300,7 +300,7 @@ static const int tcg_target_reg_alloc_order[] = {
> #endif
> };
>
> -#if MAX_OPC_PARAM_IARGS != 4
> +#if MAX_OPC_PARAM_IARGS != 5
> # error Fix needed, number of supported input arguments changed!
> #endif
>
> @@ -309,16 +309,18 @@ static const int tcg_target_call_iarg_regs[] = {
> TCG_REG_R1,
> TCG_REG_R2,
> TCG_REG_R3,
> -#if TCG_TARGET_REG_BITS == 32
> - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
> #if 0 /* used for TCG_REG_CALL_STACK */
> TCG_REG_R4,
> #endif
> TCG_REG_R5,
> +#if TCG_TARGET_REG_BITS == 32
> + /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
> TCG_REG_R6,
> TCG_REG_R7,
> #if TCG_TARGET_NB_REGS >= 16
> TCG_REG_R8,
> + TCG_REG_R9,
> + TCG_REG_R10,
> #else
> # error Too few input registers available
> #endif
> @@ -798,7 +800,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_qemu_st8:
> case INDEX_op_qemu_st16:
> case INDEX_op_qemu_st32:
> - tcg_out_r(s, TCG_AREG0);
> tcg_out_r(s, *args++);
> tcg_out_r(s, *args++);
> #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
> @@ -809,7 +810,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> #endif
> break;
> case INDEX_op_qemu_st64:
> - tcg_out_r(s, TCG_AREG0);
> tcg_out_r(s, *args++);
> #if TCG_TARGET_REG_BITS == 32
> tcg_out_r(s, *args++);
> diff --git a/tci.c b/tci.c
> index ce8a988..a4f7b78 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -36,17 +36,19 @@
> tcg_abort(); \
> } while (0)
>
> -#if MAX_OPC_PARAM_IARGS != 4
> +#if MAX_OPC_PARAM_IARGS != 5
> # error Fix needed, number of supported input arguments changed!
> #endif
> #if TCG_TARGET_REG_BITS == 32
> typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
> tcg_target_ulong, tcg_target_ulong,
> tcg_target_ulong, tcg_target_ulong,
> + tcg_target_ulong, tcg_target_ulong,
> tcg_target_ulong, tcg_target_ulong);
> #else
> typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
> - tcg_target_ulong, tcg_target_ulong);
> + tcg_target_ulong, tcg_target_ulong,
> + tcg_target_ulong);
> #endif
>
> /* TCI can optionally use a global register variable for env. */
> @@ -489,14 +491,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
> tci_read_reg(TCG_REG_R5),
> tci_read_reg(TCG_REG_R6),
> tci_read_reg(TCG_REG_R7),
> - tci_read_reg(TCG_REG_R8));
> + tci_read_reg(TCG_REG_R8),
> + tci_read_reg(TCG_REG_R9),
> + tci_read_reg(TCG_REG_R10));
> tci_write_reg(TCG_REG_R0, tmp64);
> tci_write_reg(TCG_REG_R1, tmp64 >> 32);
> #else
> tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
> tci_read_reg(TCG_REG_R1),
> tci_read_reg(TCG_REG_R2),
> - tci_read_reg(TCG_REG_R3));
> + tci_read_reg(TCG_REG_R3),
> + tci_read_reg(TCG_REG_R5));
> tci_write_reg(TCG_REG_R0, tmp64);
> #endif
> break;
> --
Thanks, applied.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 3+ messages in thread
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2012-09-18 20:43 [Qemu-devel] [PATCH stable] tci: Fix for AREG0 free mode Stefan Weil
2012-09-27 18:49 ` Stefan Weil
2012-09-27 19:29 ` Aurelien Jarno
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