From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47832) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE85W-0000L2-J6 for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TE85V-000557-6q for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:22 -0400 Received: from mail-lpp01m010-f45.google.com ([209.85.215.45]:61843) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE85U-00052h-V7 for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:21 -0400 Received: by mail-lpp01m010-f45.google.com with SMTP id z14so273861lag.4 for ; Tue, 18 Sep 2012 17:24:20 -0700 (PDT) From: Max Filippov Date: Wed, 19 Sep 2012 04:23:57 +0400 Message-Id: <1348014239-6233-9-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1348014239-6233-1-git-send-email-jcmvbkbc@gmail.com> References: <1348014239-6233-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH v3 08/10] target-xtensa: implement FP0 conversions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Peter Maydell , Max Filippov These are FP to integer and integer to FP conversion opcodes. See ISA, 4.3.10 for more details. Note that ISA description for utrunc.s is currently incorrect and will be fixed in future revisions. Signed-off-by: Max Filippov --- target-xtensa/helper.h | 4 +++ target-xtensa/op_helper.c | 37 ++++++++++++++++++++++++++++++++++ target-xtensa/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 0 deletions(-) diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h index 4e6e417..9557347 100644 --- a/target-xtensa/helper.h +++ b/target-xtensa/helper.h @@ -44,5 +44,9 @@ DEF_HELPER_3(sub_s, f32, env, f32, f32) DEF_HELPER_3(mul_s, f32, env, f32, f32) DEF_HELPER_4(madd_s, f32, env, f32, f32, f32) DEF_HELPER_4(msub_s, f32, env, f32, f32, f32) +DEF_HELPER_FLAGS_3(ftoi, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32) +DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32) +DEF_HELPER_3(itof, f32, env, i32, i32) +DEF_HELPER_3(uitof, f32, env, i32, i32) #include "def-helper.h" diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index ba935a8..5cf9c02 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -821,3 +821,40 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) return float32_muladd(b, c, a, float_muladd_negate_product, &env->fp_status); } + +uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = {0}; + + set_float_rounding_mode(rounding_mode, &fp_status); + return float32_to_int32( + float32_scalbn(v, scale, &fp_status), &fp_status); +} + +uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = {0}; + float32 res; + + set_float_rounding_mode(rounding_mode, &fp_status); + + res = float32_scalbn(v, scale, &fp_status); + + if (float32_is_neg(v) && !float32_is_any_nan(v)) { + return float32_to_int32(res, &fp_status); + } else { + return float32_to_uint32(res, &fp_status); + } +} + +float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_scalbn(int32_to_float32(v, &env->fp_status), + (int32_t)scale, &env->fp_status); +} + +float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_scalbn(uint32_to_float32(v, &env->fp_status), + (int32_t)scale, &env->fp_status); +} diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index a2ce286..fabde4f 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1915,6 +1915,54 @@ static void disas_xtensa_insn(DisasContext *dc) cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); break; + case 8: /*ROUND.Sf*/ + case 9: /*TRUNC.Sf*/ + case 10: /*FLOOR.Sf*/ + case 11: /*CEIL.Sf*/ + case 14: /*UTRUNC.Sf*/ + gen_window_check1(dc, RRR_R); + { + static const unsigned rounding_mode_const[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_down, + float_round_up, + [6] = float_round_to_zero, + }; + TCGv_i32 rounding_mode = tcg_const_i32( + rounding_mode_const[OP2 & 7]); + TCGv_i32 scale = tcg_const_i32(RRR_T); + + if (OP2 == 14) { + gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], + rounding_mode, scale); + } else { + gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], + rounding_mode, scale); + } + + tcg_temp_free(rounding_mode); + tcg_temp_free(scale); + } + break; + + case 12: /*FLOAT.Sf*/ + case 13: /*UFLOAT.Sf*/ + gen_window_check1(dc, RRR_S); + { + TCGv_i32 scale = tcg_const_i32(-RRR_T); + + if (OP2 == 13) { + gen_helper_uitof(cpu_FR[RRR_R], cpu_env, + cpu_R[RRR_S], scale); + } else { + gen_helper_itof(cpu_FR[RRR_R], cpu_env, + cpu_R[RRR_S], scale); + } + tcg_temp_free(scale); + } + break; + case 15: /*FP1OP*/ switch (RRR_T) { case 0: /*MOV.Sf*/ -- 1.7.7.6