From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48755) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6KR-0006b7-D1 for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TF6KN-00084F-9w for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:47 -0400 Received: from hall.aurel32.net ([88.191.126.93]:43335) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6KN-000848-1o for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:43 -0400 From: Aurelien Jarno Date: Fri, 21 Sep 2012 18:43:20 +0200 Message-Id: <1348245809-13482-2-git-send-email-aurelien@aurel32.net> In-Reply-To: <1348245809-13482-1-git-send-email-aurelien@aurel32.net> References: <1348245809-13482-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 01/10] tcg-mips: fix wrong usage of 'Z' constraint List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno The 'Z' constraint has been introduced to map the zero register. However when the op also accept a constant, there is no point to accept the zero register in addition. Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 74db83d..9293745 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1453,24 +1453,24 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_st16_i32, { "rZ", "r" } }, { INDEX_op_st_i32, { "rZ", "r" } }, - { INDEX_op_add_i32, { "r", "rZ", "rJZ" } }, + { INDEX_op_add_i32, { "r", "rZ", "rJ" } }, { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } }, { INDEX_op_div_i32, { "r", "rZ", "rZ" } }, { INDEX_op_divu_i32, { "r", "rZ", "rZ" } }, { INDEX_op_rem_i32, { "r", "rZ", "rZ" } }, { INDEX_op_remu_i32, { "r", "rZ", "rZ" } }, - { INDEX_op_sub_i32, { "r", "rZ", "rJZ" } }, + { INDEX_op_sub_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_and_i32, { "r", "rZ", "rIZ" } }, + { INDEX_op_and_i32, { "r", "rZ", "rI" } }, { INDEX_op_nor_i32, { "r", "rZ", "rZ" } }, { INDEX_op_not_i32, { "r", "rZ" } }, { INDEX_op_or_i32, { "r", "rZ", "rIZ" } }, { INDEX_op_xor_i32, { "r", "rZ", "rIZ" } }, - { INDEX_op_shl_i32, { "r", "rZ", "riZ" } }, - { INDEX_op_shr_i32, { "r", "rZ", "riZ" } }, - { INDEX_op_sar_i32, { "r", "rZ", "riZ" } }, + { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, + { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, + { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, { INDEX_op_ext8s_i32, { "r", "rZ" } }, { INDEX_op_ext16s_i32, { "r", "rZ" } }, @@ -1479,8 +1479,8 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, - { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } }, - { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } }, + { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, + { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } }, #if TARGET_LONG_BITS == 32 -- 1.7.10.4