From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6o7-00062h-CR for qemu-devel@nongnu.org; Fri, 21 Sep 2012 13:14:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TF6o6-0003Pa-0u for qemu-devel@nongnu.org; Fri, 21 Sep 2012 13:14:27 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:43448) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6o5-0003NU-S2 for qemu-devel@nongnu.org; Fri, 21 Sep 2012 13:14:25 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so8127923pbb.4 for ; Fri, 21 Sep 2012 10:14:25 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 21 Sep 2012 10:13:40 -0700 Message-Id: <1348247620-12734-8-git-send-email-rth@twiddle.net> In-Reply-To: <1348247620-12734-1-git-send-email-rth@twiddle.net> References: <1348247620-12734-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 7/7] tcg: Streamline movcond_i64 using movcond_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno When movcond_i32 is available we can further reduce the generated op count from 12 to 6, and the generated code size on i686 from 88 to 74 bytes. Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 3e375ea..0145a09 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2147,16 +2147,24 @@ static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, TCGV_LOW(c1), TCGV_HIGH(c1), TCGV_LOW(c2), TCGV_HIGH(c2), cond); - tcg_gen_neg_i32(t0, t0); - tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); - tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); + if (TCG_TARGET_HAS_movcond_i32) { + tcg_gen_movi_i32(t1, 0); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, + TCGV_LOW(v1), TCGV_LOW(v2)); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, + TCGV_HIGH(v1), TCGV_HIGH(v2)); + } else { + tcg_gen_neg_i32(t0, t0); - tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); - tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); + tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); + tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); + tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); + tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); + tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); } else { -- 1.7.11.4