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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 1/8] tcg: Adjust descriptions of *cond opcodes
Date: Fri, 21 Sep 2012 17:18:09 -0700	[thread overview]
Message-ID: <1348273096-1495-2-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1348273096-1495-1-git-send-email-rth@twiddle.net>

The README file documented the operand ordering of the tcg_gen_*
functions.  Since we're documenting opcodes here, use the true
operand ordering.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Cc: malc <av1474@comtv.ru>
---
 tcg/README | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tcg/README b/tcg/README
index d03ae05..cd9d9cc 100644
--- a/tcg/README
+++ b/tcg/README
@@ -141,7 +141,7 @@ Define label 'label' at the current program point.
 
 Jump to label.
 
-* brcond_i32/i64 cond, t0, t1, label
+* brcond_i32/i64 t0, t1, cond, label
 
 Conditional jump if t0 cond t1 is true. cond can be:
     TCG_COND_EQ
@@ -301,13 +301,13 @@ This operation would be equivalent to
 
 ********* Conditional moves
 
-* setcond_i32/i64 cond, dest, t1, t2
+* setcond_i32/i64 dest, t1, t2, cond
 
 dest = (t1 cond t2)
 
 Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
 
-* movcond_i32/i64 cond, dest, c1, c2, v1, v2
+* movcond_i32/i64 dest, c1, c2, v1, v2, cond
 
 dest = (c1 cond c2 ? v1 : v2)
 
@@ -360,7 +360,7 @@ The following opcodes are internal to TCG.  Thus they are to be implemented by
 32-bit host code generators, but are not to be emitted by guest translators.
 They are emitted as needed by inline functions within "tcg-op.h".
 
-* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
+* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
 
 Similar to brcond, except that the 64-bit values T0 and T1
 are formed from two 32-bit arguments.
@@ -377,7 +377,7 @@ is returned in two 32-bit outputs.
 Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
 the full 64-bit product T0.  The later is returned in two 32-bit outputs.
 
-* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
+* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
 
 Similar to setcond, except that the 64-bit values T1 and T2 are
 formed from two 32-bit arguments.  The result is a 32-bit value.
-- 
1.7.11.4

  reply	other threads:[~2012-09-22  0:18 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-09-22  0:18 [Qemu-devel] [PATCH 0/8] Misc tcg improvements Richard Henderson
2012-09-22  0:18 ` Richard Henderson [this message]
2012-09-22 10:16   ` [Qemu-devel] [PATCH 1/8] tcg: Adjust descriptions of *cond opcodes malc
2012-09-22 19:51   ` Aurelien Jarno
2012-09-22  0:18 ` [Qemu-devel] [PATCH 2/8] tcg: Emit ANDI as EXTU for appropriate constants Richard Henderson
2012-09-22 19:52   ` Aurelien Jarno
2012-09-22  0:18 ` [Qemu-devel] [PATCH 3/8] tcg: Optimize initial inputs for ori_i64 Richard Henderson
2012-09-22 19:52   ` Aurelien Jarno
2012-09-22  0:18 ` [Qemu-devel] [PATCH 4/8] tcg: Emit XORI as NOT for appropriate constants Richard Henderson
2012-09-22 19:52   ` Aurelien Jarno
2012-09-22  0:18 ` [Qemu-devel] [PATCH 5/8] tcg: Implement concat*_i64 with deposit_i64 Richard Henderson
2012-09-22 19:52   ` Aurelien Jarno
2012-09-24 15:38     ` Richard Henderson
2012-09-22  0:18 ` [Qemu-devel] [PATCH 6/8] tcg: Add tcg_debug_assert Richard Henderson
2012-09-22 19:52   ` Aurelien Jarno
2012-09-22  0:18 ` [Qemu-devel] [PATCH 7/8] tcg: Sanity check deposit inputs Richard Henderson
2012-09-22 19:52   ` Aurelien Jarno
2012-09-22  0:18 ` [Qemu-devel] [PATCH 8/8] tcg: Sanity check goto_tb input Richard Henderson
2012-09-22 13:06   ` Max Filippov
2012-09-22 19:52   ` Aurelien Jarno
2012-09-25 22:48 ` [Qemu-devel] [PATCH 0/8] Misc tcg improvements Aurelien Jarno

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