From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFEnp-0000aL-Sz for qemu-devel@nongnu.org; Fri, 21 Sep 2012 21:46:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFEno-0003fS-KE for qemu-devel@nongnu.org; Fri, 21 Sep 2012 21:46:41 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:36846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFEno-0003fO-DF for qemu-devel@nongnu.org; Fri, 21 Sep 2012 21:46:40 -0400 Received: by padfb10 with SMTP id fb10so612380pad.4 for ; Fri, 21 Sep 2012 18:46:39 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 21 Sep 2012 18:46:32 -0700 Message-Id: <1348278392-3075-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH] tcg-hppa: Implement movcond List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Signed-off-by: Richard Henderson --- tcg/hppa/tcg-target.c | 21 +++++++++++++++++++++ tcg/hppa/tcg-target.h | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c index 5385d45..793b90d 100644 --- a/tcg/hppa/tcg-target.c +++ b/tcg/hppa/tcg-target.c @@ -912,6 +912,18 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret, tcg_out_mov(s, TCG_TYPE_I32, ret, scratch); } +static void tcg_out_movcond(TCGContext *s, int cond, TCGArg ret, + TCGArg c1, TCGArg c2, int c2const, + TCGArg v1, int v1const) +{ + tcg_out_comclr(s, tcg_invert_cond(cond), TCG_REG_R0, c1, c2, c2const); + if (v1const) { + tcg_out_movi(s, TCG_TYPE_I32, ret, v1); + } else { + tcg_out_mov(s, TCG_TYPE_I32, ret, v1); + } +} + #if defined(CONFIG_SOFTMMU) #include "../../softmmu_defs.h" @@ -1520,6 +1532,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, args[3], const_args[3], args[4], const_args[4]); break; + case INDEX_op_movcond_i32: + tcg_out_movcond(s, args[5], args[0], args[1], args[2], const_args[2], + args[3], const_args[3]); + break; + case INDEX_op_add2_i32: tcg_out_add2(s, args[0], args[1], args[2], args[3], args[4], args[5], const_args[4]); @@ -1628,6 +1645,10 @@ static const TCGTargetOpDef hppa_op_defs[] = { { INDEX_op_setcond_i32, { "r", "rZ", "rI" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rI", "rI" } }, + /* ??? We can actually support a signed 14-bit arg3, but we + only have existing constraints for a signed 11-bit. */ + { INDEX_op_movcond_i32, { "r", "rZ", "rI", "rI", "0" } }, + { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rI", "rZ" } }, { INDEX_op_sub2_i32, { "r", "r", "rI", "rZ", "rK", "rZ" } }, diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h index 4defd28..5351353 100644 --- a/tcg/hppa/tcg-target.h +++ b/tcg/hppa/tcg-target.h @@ -96,7 +96,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 /* optional instructions automatically implemented */ #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, 0, rs */ -- 1.7.11.4