From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5x-0005Qf-Jq for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFF5v-0000oJ-QG for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:25 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:56041) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5v-0000d6-L2 for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:23 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so8850154pbb.4 for ; Fri, 21 Sep 2012 19:05:23 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 21 Sep 2012 19:05:03 -0700 Message-Id: <1348279507-3617-11-git-send-email-rth@twiddle.net> In-Reply-To: <1348279507-3617-1-git-send-email-rth@twiddle.net> References: <1348279507-3617-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 10/14] tcg-sparc: Mask shift immediates to avoid illegal insns. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index e625aa3..be5c170 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, goto gen_arith; case INDEX_op_shl_i32: c = SHIFT_SLL; - goto gen_arith; + do_shift32: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c); + break; case INDEX_op_shr_i32: c = SHIFT_SRL; - goto gen_arith; + goto do_shift32; case INDEX_op_sar_i32: c = SHIFT_SRA; - goto gen_arith; + goto do_shift32; case INDEX_op_mul_i32: c = ARITH_UMUL; goto gen_arith; @@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_shl_i64: c = SHIFT_SLLX; - goto gen_arith; + do_shift64: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c); + break; case INDEX_op_shr_i64: c = SHIFT_SRLX; - goto gen_arith; + goto do_shift64; case INDEX_op_sar_i64: c = SHIFT_SRAX; - goto gen_arith; + goto do_shift64; case INDEX_op_mul_i64: c = ARITH_MULX; goto gen_arith; -- 1.7.11.4