* [Qemu-devel] [PATCH 1/7] Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
@ 2012-09-24 21:55 ` Richard Henderson
2012-09-25 22:44 ` Aurelien Jarno
2012-09-24 21:55 ` [Qemu-devel] [PATCH 2/7] target-m68k: Call tcg_gen_debug_insn_start Richard Henderson
` (7 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2012-09-24 21:55 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/translate.c | 2 +-
target-arm/translate.c | 2 +-
target-cris/translate.c | 3 ++-
target-i386/translate.c | 3 ++-
target-lm32/translate.c | 2 +-
target-microblaze/translate.c | 3 ++-
target-mips/translate.c | 3 ++-
target-openrisc/translate.c | 2 +-
target-ppc/translate.c | 3 ++-
target-sh4/translate.c | 2 +-
target-sparc/translate.c | 3 ++-
target-xtensa/translate.c | 2 +-
12 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 4a9011a..4194d6e 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3421,7 +3421,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
insn = cpu_ldl_code(env, ctx.pc);
num_insns++;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx.pc);
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f4b447a..5fded49 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9816,7 +9816,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
}
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 19144b5..755de65 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3074,8 +3074,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
int insn_len = 2;
int i;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
+ }
/* Load a halfword onto the instruction register. */
dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index eb0cabc..323869d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4202,8 +4202,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
target_ulong next_eip, tval;
int rex_w, rex_r;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(pc_start);
+ }
s->pc = pc_start;
prefixes = 0;
aflag = s->code32;
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 5f6dcba..77c2866 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -942,7 +942,7 @@ static const DecoderInfo decinfo[] = {
static inline void decode(DisasContext *dc, uint32_t ir)
{
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
}
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 9c7d77f..7d864b1 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1664,8 +1664,9 @@ static inline void decode(DisasContext *dc, uint32_t ir)
{
int i;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
+ }
dc->ir = ir;
LOG_DIS("%8.8x\t", dc->ir);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index fa79d49..454e5cc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12124,8 +12124,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
gen_set_label(l1);
}
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx->pc);
+ }
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 325ba09..e2cad3a 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1715,7 +1715,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
gen_opc_icount[k] = num_insns;
}
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ac915cc..1042268 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9690,8 +9690,9 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env,
LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), little_endian ? "little" : "big");
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx.nip);
+ }
ctx.nip += 4;
table = env->opcodes;
num_insns++;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 0fa83ca..9d955eb 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1924,7 +1924,7 @@ static void decode_opc(DisasContext * ctx)
{
uint32_t old_flags = ctx->flags;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx->pc);
}
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index b95f91c..e5ebedf 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2394,8 +2394,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
target_long simm;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
+ }
opc = GET_FIELD(insn, 0, 1);
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index ba3ffcb..b9acd70 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2923,7 +2923,7 @@ static void gen_intermediate_code_internal(
gen_opc_icount[lj] = insn_count;
}
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc.pc);
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 1/7] Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
2012-09-24 21:55 ` [Qemu-devel] [PATCH 1/7] Emit debug_insn for CPU_LOG_TB_OP_OPT as well Richard Henderson
@ 2012-09-25 22:44 ` Aurelien Jarno
0 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-25 22:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Mon, Sep 24, 2012 at 02:55:47PM -0700, Richard Henderson wrote:
> For all targets that currently call tcg_gen_debug_insn_start,
> add CPU_LOG_TB_OP_OPT to the condition that gates it.
>
> This is useful for comparing optimization dumps, when the
> pre-optimization dump is merely noise.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-alpha/translate.c | 2 +-
> target-arm/translate.c | 2 +-
> target-cris/translate.c | 3 ++-
> target-i386/translate.c | 3 ++-
> target-lm32/translate.c | 2 +-
> target-microblaze/translate.c | 3 ++-
> target-mips/translate.c | 3 ++-
> target-openrisc/translate.c | 2 +-
> target-ppc/translate.c | 3 ++-
> target-sh4/translate.c | 2 +-
> target-sparc/translate.c | 3 ++-
> target-xtensa/translate.c | 2 +-
> 12 files changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/target-alpha/translate.c b/target-alpha/translate.c
> index 4a9011a..4194d6e 100644
> --- a/target-alpha/translate.c
> +++ b/target-alpha/translate.c
> @@ -3421,7 +3421,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
> insn = cpu_ldl_code(env, ctx.pc);
> num_insns++;
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(ctx.pc);
> }
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index f4b447a..5fded49 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -9816,7 +9816,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
> if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
> gen_io_start();
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(dc->pc);
> }
>
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index 19144b5..755de65 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -3074,8 +3074,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
> int insn_len = 2;
> int i;
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(dc->pc);
> + }
>
> /* Load a halfword onto the instruction register. */
> dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index eb0cabc..323869d 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -4202,8 +4202,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
> target_ulong next_eip, tval;
> int rex_w, rex_r;
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(pc_start);
> + }
> s->pc = pc_start;
> prefixes = 0;
> aflag = s->code32;
> diff --git a/target-lm32/translate.c b/target-lm32/translate.c
> index 5f6dcba..77c2866 100644
> --- a/target-lm32/translate.c
> +++ b/target-lm32/translate.c
> @@ -942,7 +942,7 @@ static const DecoderInfo decinfo[] = {
>
> static inline void decode(DisasContext *dc, uint32_t ir)
> {
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(dc->pc);
> }
>
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 9c7d77f..7d864b1 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1664,8 +1664,9 @@ static inline void decode(DisasContext *dc, uint32_t ir)
> {
> int i;
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(dc->pc);
> + }
>
> dc->ir = ir;
> LOG_DIS("%8.8x\t", dc->ir);
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index fa79d49..454e5cc 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -12124,8 +12124,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
> gen_set_label(l1);
> }
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(ctx->pc);
> + }
>
> op = MASK_OP_MAJOR(ctx->opcode);
> rs = (ctx->opcode >> 21) & 0x1f;
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index 325ba09..e2cad3a 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -1715,7 +1715,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
> gen_opc_icount[k] = num_insns;
> }
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(dc->pc);
> }
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index ac915cc..1042268 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -9690,8 +9690,9 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env,
> LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
> ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
> opc3(ctx.opcode), little_endian ? "little" : "big");
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(ctx.nip);
> + }
> ctx.nip += 4;
> table = env->opcodes;
> num_insns++;
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 0fa83ca..9d955eb 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -1924,7 +1924,7 @@ static void decode_opc(DisasContext * ctx)
> {
> uint32_t old_flags = ctx->flags;
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(ctx->pc);
> }
>
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index b95f91c..e5ebedf 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -2394,8 +2394,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
> target_long simm;
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(dc->pc);
> + }
>
> opc = GET_FIELD(insn, 0, 1);
>
> diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
> index ba3ffcb..b9acd70 100644
> --- a/target-xtensa/translate.c
> +++ b/target-xtensa/translate.c
> @@ -2923,7 +2923,7 @@ static void gen_intermediate_code_internal(
> gen_opc_icount[lj] = insn_count;
> }
>
> - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> tcg_gen_debug_insn_start(dc.pc);
> }
>
> --
> 1.7.11.4
>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 2/7] target-m68k: Call tcg_gen_debug_insn_start
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
2012-09-24 21:55 ` [Qemu-devel] [PATCH 1/7] Emit debug_insn for CPU_LOG_TB_OP_OPT as well Richard Henderson
@ 2012-09-24 21:55 ` Richard Henderson
2012-09-25 22:44 ` Aurelien Jarno
2012-09-24 21:55 ` [Qemu-devel] [PATCH 3/7] target-s390x: " Richard Henderson
` (6 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2012-09-24 21:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, aurelien
Cc: Paul Brook <paul@codesourcery.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-m68k/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index fb707f2..451ef74 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2953,6 +2953,10 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
{
uint16_t insn;
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
+ tcg_gen_debug_insn_start(s->pc);
+ }
+
insn = cpu_lduw_code(env, s->pc);
s->pc += 2;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 2/7] target-m68k: Call tcg_gen_debug_insn_start
2012-09-24 21:55 ` [Qemu-devel] [PATCH 2/7] target-m68k: Call tcg_gen_debug_insn_start Richard Henderson
@ 2012-09-25 22:44 ` Aurelien Jarno
0 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-25 22:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Paul Brook
On Mon, Sep 24, 2012 at 02:55:48PM -0700, Richard Henderson wrote:
> Cc: Paul Brook <paul@codesourcery.com>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-m68k/translate.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index fb707f2..451ef74 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c
> @@ -2953,6 +2953,10 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
> {
> uint16_t insn;
>
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> + tcg_gen_debug_insn_start(s->pc);
> + }
> +
> insn = cpu_lduw_code(env, s->pc);
> s->pc += 2;
>
> --
> 1.7.11.4
>
>
>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 3/7] target-s390x: Call tcg_gen_debug_insn_start
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
2012-09-24 21:55 ` [Qemu-devel] [PATCH 1/7] Emit debug_insn for CPU_LOG_TB_OP_OPT as well Richard Henderson
2012-09-24 21:55 ` [Qemu-devel] [PATCH 2/7] target-m68k: Call tcg_gen_debug_insn_start Richard Henderson
@ 2012-09-24 21:55 ` Richard Henderson
2012-09-25 22:44 ` Aurelien Jarno
2012-09-24 21:55 ` [Qemu-devel] [PATCH 4/7] target-unicore32: " Richard Henderson
` (5 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2012-09-24 21:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Graf, aurelien
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-s390x/translate.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 3214783..6fa76a0 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5173,10 +5173,11 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env,
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
-#if defined(S390X_DEBUG_DISAS_VERBOSE)
- LOG_DISAS("pc " TARGET_FMT_lx "\n",
- dc.pc);
-#endif
+
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
+ tcg_gen_debug_insn_start(dc.pc);
+ }
+
disas_s390_insn(env, &dc);
num_insns++;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 3/7] target-s390x: Call tcg_gen_debug_insn_start
2012-09-24 21:55 ` [Qemu-devel] [PATCH 3/7] target-s390x: " Richard Henderson
@ 2012-09-25 22:44 ` Aurelien Jarno
0 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-25 22:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Alexander Graf
On Mon, Sep 24, 2012 at 02:55:49PM -0700, Richard Henderson wrote:
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-s390x/translate.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/target-s390x/translate.c b/target-s390x/translate.c
> index 3214783..6fa76a0 100644
> --- a/target-s390x/translate.c
> +++ b/target-s390x/translate.c
> @@ -5173,10 +5173,11 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env,
> if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
> gen_io_start();
> }
> -#if defined(S390X_DEBUG_DISAS_VERBOSE)
> - LOG_DISAS("pc " TARGET_FMT_lx "\n",
> - dc.pc);
> -#endif
> +
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> + tcg_gen_debug_insn_start(dc.pc);
> + }
> +
> disas_s390_insn(env, &dc);
>
> num_insns++;
> --
> 1.7.11.4
>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 4/7] target-unicore32: Call tcg_gen_debug_insn_start
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
` (2 preceding siblings ...)
2012-09-24 21:55 ` [Qemu-devel] [PATCH 3/7] target-s390x: " Richard Henderson
@ 2012-09-24 21:55 ` Richard Henderson
2012-09-25 22:45 ` Aurelien Jarno
2012-09-24 21:55 ` [Qemu-devel] [PATCH 5/7] target-s390x: Use CPU_LOG_INT Richard Henderson
` (4 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2012-09-24 21:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, aurelien
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-unicore32/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index b786a6b..36f4f2f 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1861,6 +1861,10 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
{
unsigned int insn;
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
+ tcg_gen_debug_insn_start(s->pc);
+ }
+
insn = cpu_ldl_code(env, s->pc);
s->pc += 4;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 4/7] target-unicore32: Call tcg_gen_debug_insn_start
2012-09-24 21:55 ` [Qemu-devel] [PATCH 4/7] target-unicore32: " Richard Henderson
@ 2012-09-25 22:45 ` Aurelien Jarno
0 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-25 22:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: Guan Xuetao, qemu-devel
On Mon, Sep 24, 2012 at 02:55:50PM -0700, Richard Henderson wrote:
> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-unicore32/translate.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index b786a6b..36f4f2f 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -1861,6 +1861,10 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
> {
> unsigned int insn;
>
> + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> + tcg_gen_debug_insn_start(s->pc);
> + }
> +
> insn = cpu_ldl_code(env, s->pc);
> s->pc += 4;
>
> --
> 1.7.11.4
>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 5/7] target-s390x: Use CPU_LOG_INT
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
` (3 preceding siblings ...)
2012-09-24 21:55 ` [Qemu-devel] [PATCH 4/7] target-unicore32: " Richard Henderson
@ 2012-09-24 21:55 ` Richard Henderson
2012-09-25 22:45 ` Aurelien Jarno
2012-09-24 21:55 ` [Qemu-devel] [PATCH 6/7] target-s390x: Avoid double CPU_LOG_TB_CPU Richard Henderson
` (3 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2012-09-24 21:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Graf, aurelien
Three places in the interrupt code did we not honor the mask.
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-s390x/helper.c | 7 ++++---
target-s390x/misc_helper.c | 3 ++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index a5741ec..22256b0 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -511,7 +511,8 @@ static void do_program_interrupt(CPUS390XState *env)
break;
}
- qemu_log("%s: code=0x%x ilc=%d\n", __func__, env->int_pgm_code, ilc);
+ qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilc=%d\n",
+ __func__, env->int_pgm_code, ilc);
lowcore = cpu_physical_memory_map(env->psa, &len, 1);
@@ -575,8 +576,8 @@ static void do_ext_interrupt(CPUS390XState *env)
void do_interrupt(CPUS390XState *env)
{
- qemu_log("%s: %d at pc=%" PRIx64 "\n", __func__, env->exception_index,
- env->psw.addr);
+ qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
+ __func__, env->exception_index, env->psw.addr);
s390_add_running_cpu(env);
/* handle external interrupts */
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index 2938ac9..e9b3cae 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -53,7 +53,8 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp)
#ifndef CONFIG_USER_ONLY
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{
- qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
+ qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
+ env->psw.addr);
if (kvm_enabled()) {
#ifdef CONFIG_KVM
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 5/7] target-s390x: Use CPU_LOG_INT
2012-09-24 21:55 ` [Qemu-devel] [PATCH 5/7] target-s390x: Use CPU_LOG_INT Richard Henderson
@ 2012-09-25 22:45 ` Aurelien Jarno
0 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-25 22:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Alexander Graf
On Mon, Sep 24, 2012 at 02:55:51PM -0700, Richard Henderson wrote:
> Three places in the interrupt code did we not honor the mask.
>
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-s390x/helper.c | 7 ++++---
> target-s390x/misc_helper.c | 3 ++-
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index a5741ec..22256b0 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -511,7 +511,8 @@ static void do_program_interrupt(CPUS390XState *env)
> break;
> }
>
> - qemu_log("%s: code=0x%x ilc=%d\n", __func__, env->int_pgm_code, ilc);
> + qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilc=%d\n",
> + __func__, env->int_pgm_code, ilc);
>
> lowcore = cpu_physical_memory_map(env->psa, &len, 1);
>
> @@ -575,8 +576,8 @@ static void do_ext_interrupt(CPUS390XState *env)
>
> void do_interrupt(CPUS390XState *env)
> {
> - qemu_log("%s: %d at pc=%" PRIx64 "\n", __func__, env->exception_index,
> - env->psw.addr);
> + qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
> + __func__, env->exception_index, env->psw.addr);
>
> s390_add_running_cpu(env);
> /* handle external interrupts */
> diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
> index 2938ac9..e9b3cae 100644
> --- a/target-s390x/misc_helper.c
> +++ b/target-s390x/misc_helper.c
> @@ -53,7 +53,8 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp)
> #ifndef CONFIG_USER_ONLY
> void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
> {
> - qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
> + qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
> + env->psw.addr);
>
> if (kvm_enabled()) {
> #ifdef CONFIG_KVM
> --
> 1.7.11.4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 6/7] target-s390x: Avoid double CPU_LOG_TB_CPU
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
` (4 preceding siblings ...)
2012-09-24 21:55 ` [Qemu-devel] [PATCH 5/7] target-s390x: Use CPU_LOG_INT Richard Henderson
@ 2012-09-24 21:55 ` Richard Henderson
2012-09-25 22:45 ` Aurelien Jarno
2012-09-24 21:55 ` [Qemu-devel] [PATCH 7/7] target-s390x: Tidy cpu_dump_state Richard Henderson
` (2 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2012-09-24 21:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Graf, aurelien
This is already handled generically in cpu_exec.
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-s390x/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 6fa76a0..4cc9225 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5220,7 +5220,6 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env,
tb->icount = num_insns;
}
#if defined(S390X_DEBUG_DISAS)
- log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(pc_start, dc.pc - pc_start, 1);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 6/7] target-s390x: Avoid double CPU_LOG_TB_CPU
2012-09-24 21:55 ` [Qemu-devel] [PATCH 6/7] target-s390x: Avoid double CPU_LOG_TB_CPU Richard Henderson
@ 2012-09-25 22:45 ` Aurelien Jarno
0 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-25 22:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Alexander Graf
On Mon, Sep 24, 2012 at 02:55:52PM -0700, Richard Henderson wrote:
> This is already handled generically in cpu_exec.
>
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-s390x/translate.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target-s390x/translate.c b/target-s390x/translate.c
> index 6fa76a0..4cc9225 100644
> --- a/target-s390x/translate.c
> +++ b/target-s390x/translate.c
> @@ -5220,7 +5220,6 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env,
> tb->icount = num_insns;
> }
> #if defined(S390X_DEBUG_DISAS)
> - log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> log_target_disas(pc_start, dc.pc - pc_start, 1);
> --
> 1.7.11.4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 7/7] target-s390x: Tidy cpu_dump_state
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
` (5 preceding siblings ...)
2012-09-24 21:55 ` [Qemu-devel] [PATCH 6/7] target-s390x: Avoid double CPU_LOG_TB_CPU Richard Henderson
@ 2012-09-24 21:55 ` Richard Henderson
2012-09-25 22:45 ` Aurelien Jarno
2012-09-25 7:40 ` [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Alexander Graf
2012-09-27 19:47 ` Aurelien Jarno
8 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2012-09-24 21:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Graf, aurelien
The blank lines inside the single dump make it difficult for the
eye to pick out the block. Worse, with interior newlines, but
no blank line following, the PSW line appears to belong to the
next dump block.
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-s390x/translate.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 4cc9225..db464cc 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -79,6 +79,14 @@ void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
{
int i;
+ if (env->cc_op > 3) {
+ cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
+ env->psw.mask, env->psw.addr, cc_name(env->cc_op));
+ } else {
+ cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
+ env->psw.mask, env->psw.addr, env->cc_op);
+ }
+
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
if ((i % 4) == 3) {
@@ -97,8 +105,6 @@ void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
}
}
- cpu_fprintf(f, "\n");
-
#ifndef CONFIG_USER_ONLY
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
@@ -110,22 +116,14 @@ void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
}
#endif
- cpu_fprintf(f, "\n");
-
- if (env->cc_op > 3) {
- cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
- env->psw.mask, env->psw.addr, cc_name(env->cc_op));
- } else {
- cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
- env->psw.mask, env->psw.addr, env->cc_op);
- }
-
#ifdef DEBUG_INLINE_BRANCHES
for (i = 0; i < CC_OP_MAX; i++) {
cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
inline_branch_miss[i], inline_branch_hit[i]);
}
#endif
+
+ cpu_fprintf(f, "\n");
}
static TCGv_i64 psw_addr;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 7/7] target-s390x: Tidy cpu_dump_state
2012-09-24 21:55 ` [Qemu-devel] [PATCH 7/7] target-s390x: Tidy cpu_dump_state Richard Henderson
@ 2012-09-25 22:45 ` Aurelien Jarno
0 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-25 22:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Alexander Graf
On Mon, Sep 24, 2012 at 02:55:53PM -0700, Richard Henderson wrote:
> The blank lines inside the single dump make it difficult for the
> eye to pick out the block. Worse, with interior newlines, but
> no blank line following, the PSW line appears to belong to the
> next dump block.
>
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-s390x/translate.c | 22 ++++++++++------------
> 1 file changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/target-s390x/translate.c b/target-s390x/translate.c
> index 4cc9225..db464cc 100644
> --- a/target-s390x/translate.c
> +++ b/target-s390x/translate.c
> @@ -79,6 +79,14 @@ void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
> {
> int i;
>
> + if (env->cc_op > 3) {
> + cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
> + env->psw.mask, env->psw.addr, cc_name(env->cc_op));
> + } else {
> + cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
> + env->psw.mask, env->psw.addr, env->cc_op);
> + }
> +
> for (i = 0; i < 16; i++) {
> cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
> if ((i % 4) == 3) {
> @@ -97,8 +105,6 @@ void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
> }
> }
>
> - cpu_fprintf(f, "\n");
> -
> #ifndef CONFIG_USER_ONLY
> for (i = 0; i < 16; i++) {
> cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
> @@ -110,22 +116,14 @@ void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
> }
> #endif
>
> - cpu_fprintf(f, "\n");
> -
> - if (env->cc_op > 3) {
> - cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
> - env->psw.mask, env->psw.addr, cc_name(env->cc_op));
> - } else {
> - cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
> - env->psw.mask, env->psw.addr, env->cc_op);
> - }
> -
> #ifdef DEBUG_INLINE_BRANCHES
> for (i = 0; i < CC_OP_MAX; i++) {
> cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
> inline_branch_miss[i], inline_branch_hit[i]);
> }
> #endif
> +
> + cpu_fprintf(f, "\n");
> }
>
> static TCGv_i64 psw_addr;
> --
> 1.7.11.4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
` (6 preceding siblings ...)
2012-09-24 21:55 ` [Qemu-devel] [PATCH 7/7] target-s390x: Tidy cpu_dump_state Richard Henderson
@ 2012-09-25 7:40 ` Alexander Graf
2012-09-27 19:47 ` Aurelien Jarno
8 siblings, 0 replies; 17+ messages in thread
From: Alexander Graf @ 2012-09-25 7:40 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, aurelien
On 24.09.2012, at 23:55, Richard Henderson wrote:
> The first patch applies to most targets, in wanting to produce
> good dumps for -d op_opt without -d op.
>
> The next three add dump_insn support to the targets lacking it.
>
> The final three fix irritations that apply to s390x. I didn't
> survey the other targets for similar mistakes.
The s390 specific patches look good to me. For those:
Reviewed-by: Alexander Graf <agraf@suse.de>
Alex
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu
2012-09-24 21:55 [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Richard Henderson
` (7 preceding siblings ...)
2012-09-25 7:40 ` [Qemu-devel] [PATCH 0/7] Tidy -d op_opt,int,cpu Alexander Graf
@ 2012-09-27 19:47 ` Aurelien Jarno
8 siblings, 0 replies; 17+ messages in thread
From: Aurelien Jarno @ 2012-09-27 19:47 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Mon, Sep 24, 2012 at 02:55:46PM -0700, Richard Henderson wrote:
> The first patch applies to most targets, in wanting to produce
> good dumps for -d op_opt without -d op.
>
> The next three add dump_insn support to the targets lacking it.
>
> The final three fix irritations that apply to s390x. I didn't
> survey the other targets for similar mistakes.
>
>
> r~
>
>
> Richard Henderson (7):
> Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
> target-m68k: Call tcg_gen_debug_insn_start
> target-s390x: Call tcg_gen_debug_insn_start
> target-unicore32: Call tcg_gen_debug_insn_start
> target-s390x: Use CPU_LOG_INT
> target-s390x: Avoid double CPU_LOG_TB_CPU
> target-s390x: Tidy cpu_dump_state
>
> target-alpha/translate.c | 2 +-
> target-arm/translate.c | 2 +-
> target-cris/translate.c | 3 ++-
> target-i386/translate.c | 3 ++-
> target-lm32/translate.c | 2 +-
> target-m68k/translate.c | 4 ++++
> target-microblaze/translate.c | 3 ++-
> target-mips/translate.c | 3 ++-
> target-openrisc/translate.c | 2 +-
> target-ppc/translate.c | 3 ++-
> target-s390x/helper.c | 7 ++++---
> target-s390x/misc_helper.c | 3 ++-
> target-s390x/translate.c | 32 +++++++++++++++-----------------
> target-sh4/translate.c | 2 +-
> target-sparc/translate.c | 3 ++-
> target-unicore32/translate.c | 4 ++++
> target-xtensa/translate.c | 2 +-
> 17 files changed, 47 insertions(+), 33 deletions(-)
>
Thanks, all applied.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
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