From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56755) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGuFC-0004Bx-LR for qemu-devel@nongnu.org; Wed, 26 Sep 2012 12:13:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TGuF6-0003H0-UL for qemu-devel@nongnu.org; Wed, 26 Sep 2012 12:13:50 -0400 Received: from 38.0.169.217.in-addr.arpa ([217.169.0.38]:53863 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGuF6-0003FA-NI for qemu-devel@nongnu.org; Wed, 26 Sep 2012 12:13:44 -0400 From: Peter Maydell Date: Wed, 26 Sep 2012 17:13:34 +0100 Message-Id: <1348676015-16547-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1348676015-16547-1-git-send-email-peter.maydell@linaro.org> References: <1348676015-16547-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/4] Versatile Express: Fix NOR flash 0 address and remove flash alias List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org, Paul Brook From: Francesco Lavra In the A series memory map (implemented in the Cortex A15 CoreTile), the first NOR flash bank (flash 0) is mapped to address 0x08000000, while address 0x00000000 can be configured as alias to either the first or the second flash bank. This patch fixes the definition of flash 0 address, and for simplicity removes the alias definition. Signed-off-by: Francesco Lavra Signed-off-by: Peter Maydell --- hw/vexpress.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/vexpress.c b/hw/vexpress.c index b615844..454c2bb 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -62,7 +62,6 @@ enum { VE_COMPACTFLASH, VE_CLCD, VE_NORFLASH0, - VE_NORFLASH0ALIAS, VE_NORFLASH1, VE_SRAM, VE_VIDEORAM, @@ -104,9 +103,8 @@ static target_phys_addr_t motherboard_legacy_map[] = { }; static target_phys_addr_t motherboard_aseries_map[] = { - /* CS0: 0x00000000 .. 0x0c000000 */ - [VE_NORFLASH0] = 0x00000000, - [VE_NORFLASH0ALIAS] = 0x08000000, + /* CS0: 0x08000000 .. 0x0c000000 */ + [VE_NORFLASH0] = 0x08000000, /* CS4: 0x0c000000 .. 0x10000000 */ [VE_NORFLASH1] = 0x0c000000, /* CS5: 0x10000000 .. 0x14000000 */ @@ -413,7 +411,6 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); /* VE_NORFLASH0: not modelled */ - /* VE_NORFLASH0ALIAS: not modelled */ /* VE_NORFLASH1: not modelled */ sram_size = 0x2000000; -- 1.7.9.5