[Qemu-devel] [PULL 0/4] arm-devs queue

[Qemu-devel] [PULL 0/4] arm-devs queue

[Peter Maydell]

Not much in this pullreq but I realised I'd been sitting on the PL190
and NVIC fixes for nearly a month :-(   Please pull.

thanks
-- PMM


The following changes since commit ac05f3492421caeb05809ffa02c6198ede179e43:

  add a boot parameter to set reboot timeout (2012-09-25 20:05:04 -0500)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git arm-devs.for-upstream

for you to fetch changes up to 3dc3e7dd936f2e7f3e6dd4056f81c8961dc8201b:

  Versatile Express: Add modelling of NOR flash (2012-09-26 16:48:21 +0100)

----------------------------------------------------------------
Brendan Fennell (1):
      pl190: fix read of VECTADDR

Francesco Lavra (2):
      Versatile Express: Fix NOR flash 0 address and remove flash alias
      Versatile Express: Add modelling of NOR flash

Meador Inge (1):
      hw/armv7m_nvic: Correctly register GIC region when setting up NVIC

 hw/armv7m_nvic.c |    3 ++-
 hw/pl190.c       |   18 ++++++++++++------
 hw/vexpress.c    |   33 ++++++++++++++++++++++++++-------
 3 files changed, 40 insertions(+), 14 deletions(-)

[Qemu-devel] [PATCH 1/4] pl190: fix read of VECTADDR

[Peter Maydell]

From: Brendan Fennell <bfennell@skynet.ie>

Reading VECTADDR was causing us to set the current priority to
the wrong value, the most obvious effect of which was that we
would return the vector for the wrong interrupt as the result
of the read.

Signed-off-by: Brendan Fennell <bfennell@skynet.ie>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/pl190.c |   18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/hw/pl190.c b/hw/pl190.c
index cb50afb..7332f4d 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -117,12 +117,18 @@ static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
         return s->protected;
     case 12: /* VECTADDR */
         /* Read vector address at the start of an ISR.  Increases the
-           current priority level to that of the current interrupt.  */
-        for (i = 0; i < s->priority; i++)
-          {
-            if ((s->level | s->soft_level) & s->prio_mask[i])
-              break;
-          }
+         * current priority level to that of the current interrupt.
+         *
+         * Since an enabled interrupt X at priority P causes prio_mask[Y]
+         * to have bit X set for all Y > P, this loop will stop with
+         * i == the priority of the highest priority set interrupt.
+         */
+        for (i = 0; i < s->priority; i++) {
+            if ((s->level | s->soft_level) & s->prio_mask[i + 1]) {
+                break;
+            }
+        }
+
         /* Reading this value with no pending interrupts is undefined.
            We return the default address.  */
         if (i == PL190_NUM_PRIO)
-- 
1.7.9.5

[Qemu-devel] [PATCH 2/4] hw/armv7m_nvic: Correctly register GIC region when setting up NVIC

[Peter Maydell]

From: Meador Inge <meadori@codesourcery.com>

When setting up the NVIC memory regions the memory range
0x100..0xcff is aliased to an IO memory region that belongs
to the ARM GIC.  This aliased region should be added to the
NVIC memory container, but the actual GIC IO memory region
was being added instead.  This mixup was causing the wrong
IO memory access functions to be called when accessing parts
of the NVIC memory.

Signed-off-by: Meador Inge <meadori@codesourcery.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/armv7m_nvic.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 6a0832e..5c09116 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -489,7 +489,8 @@ static int armv7m_nvic_init(SysBusDevice *dev)
      */
     memory_region_init_alias(&s->gic_iomem_alias, "nvic-gic", &s->gic.iomem,
                              0x100, 0xc00);
-    memory_region_add_subregion_overlap(&s->container, 0x100, &s->gic.iomem, 1);
+    memory_region_add_subregion_overlap(&s->container, 0x100,
+                                        &s->gic_iomem_alias, 1);
     /* Map the whole thing into system memory at the location required
      * by the v7M architecture.
      */
-- 
1.7.9.5

[Qemu-devel] [PATCH 3/4] Versatile Express: Fix NOR flash 0 address and remove flash alias

[Peter Maydell]

From: Francesco Lavra <francescolavra.fl@gmail.com>

In the A series memory map (implemented in the Cortex A15 CoreTile), the
first NOR flash bank (flash 0) is mapped to address 0x08000000, while
address 0x00000000 can be configured as alias to either the first or the
second flash bank. This patch fixes the definition of flash 0 address,
and for simplicity removes the alias definition.

Signed-off-by: Francesco Lavra <francescolavra.fl@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/vexpress.c |    7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/hw/vexpress.c b/hw/vexpress.c
index b615844..454c2bb 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -62,7 +62,6 @@ enum {
     VE_COMPACTFLASH,
     VE_CLCD,
     VE_NORFLASH0,
-    VE_NORFLASH0ALIAS,
     VE_NORFLASH1,
     VE_SRAM,
     VE_VIDEORAM,
@@ -104,9 +103,8 @@ static target_phys_addr_t motherboard_legacy_map[] = {
 };
 
 static target_phys_addr_t motherboard_aseries_map[] = {
-    /* CS0: 0x00000000 .. 0x0c000000 */
-    [VE_NORFLASH0] = 0x00000000,
-    [VE_NORFLASH0ALIAS] = 0x08000000,
+    /* CS0: 0x08000000 .. 0x0c000000 */
+    [VE_NORFLASH0] = 0x08000000,
     /* CS4: 0x0c000000 .. 0x10000000 */
     [VE_NORFLASH1] = 0x0c000000,
     /* CS5: 0x10000000 .. 0x14000000 */
@@ -413,7 +411,6 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 
     /* VE_NORFLASH0: not modelled */
-    /* VE_NORFLASH0ALIAS: not modelled */
     /* VE_NORFLASH1: not modelled */
 
     sram_size = 0x2000000;
-- 
1.7.9.5

[Qemu-devel] [PATCH 4/4] Versatile Express: Add modelling of NOR flash

[Peter Maydell]

From: Francesco Lavra <francescolavra.fl@gmail.com>

This patch adds modelling of the two NOR flash banks found on the
Versatile Express motherboard. Tested with U-Boot running on an emulated
Versatile Express, with either A9 or A15 CoreTile.

Signed-off-by: Francesco Lavra <francescolavra.fl@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/vexpress.c |   26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/hw/vexpress.c b/hw/vexpress.c
index 454c2bb..3596d1e 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -29,8 +29,12 @@
 #include "sysemu.h"
 #include "boards.h"
 #include "exec-memory.h"
+#include "blockdev.h"
+#include "flash.h"
 
 #define VEXPRESS_BOARD_ID 0x8e0
+#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
+#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
 
 static struct arm_boot_info vexpress_binfo;
 
@@ -355,6 +359,7 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
     qemu_irq pic[64];
     uint32_t proc_id;
     uint32_t sys_id;
+    DriveInfo *dinfo;
     ram_addr_t vram_size, sram_size;
     MemoryRegion *sysmem = get_system_memory();
     MemoryRegion *vram = g_new(MemoryRegion, 1);
@@ -410,8 +415,25 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
 
     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 
-    /* VE_NORFLASH0: not modelled */
-    /* VE_NORFLASH1: not modelled */
+    dinfo = drive_get_next(IF_PFLASH);
+    if (!pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
+            VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
+            VEXPRESS_FLASH_SECT_SIZE,
+            VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
+            0x00, 0x89, 0x00, 0x18, 0)) {
+        fprintf(stderr, "vexpress: error registering flash 0.\n");
+        exit(1);
+    }
+
+    dinfo = drive_get_next(IF_PFLASH);
+    if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1",
+            VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
+            VEXPRESS_FLASH_SECT_SIZE,
+            VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
+            0x00, 0x89, 0x00, 0x18, 0)) {
+        fprintf(stderr, "vexpress: error registering flash 1.\n");
+        exit(1);
+    }
 
     sram_size = 0x2000000;
     memory_region_init_ram(sram, "vexpress.sram", sram_size);
-- 
1.7.9.5

Re: [Qemu-devel] [PULL 0/4] arm-devs queue

[Aurelien Jarno]

On Wed, Sep 26, 2012 at 05:13:31PM +0100, Peter Maydell wrote:
> Not much in this pullreq but I realised I'd been sitting on the PL190
> and NVIC fixes for nearly a month :-(   Please pull.
> 
> thanks
> -- PMM
> 
> 
> The following changes since commit ac05f3492421caeb05809ffa02c6198ede179e43:
> 
>   add a boot parameter to set reboot timeout (2012-09-25 20:05:04 -0500)
> 
> are available in the git repository at:
> 
>   git://git.linaro.org/people/pmaydell/qemu-arm.git arm-devs.for-upstream
> 
> for you to fetch changes up to 3dc3e7dd936f2e7f3e6dd4056f81c8961dc8201b:
> 
>   Versatile Express: Add modelling of NOR flash (2012-09-26 16:48:21 +0100)
> 
> ----------------------------------------------------------------
> Brendan Fennell (1):
>       pl190: fix read of VECTADDR
> 
> Francesco Lavra (2):
>       Versatile Express: Fix NOR flash 0 address and remove flash alias
>       Versatile Express: Add modelling of NOR flash
> 
> Meador Inge (1):
>       hw/armv7m_nvic: Correctly register GIC region when setting up NVIC
> 
>  hw/armv7m_nvic.c |    3 ++-
>  hw/pl190.c       |   18 ++++++++++++------
>  hw/vexpress.c    |   33 ++++++++++++++++++++++++++-------
>  3 files changed, 40 insertions(+), 14 deletions(-)

Thanks, pulled.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net