From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGwmy-0004Ez-Bo for qemu-devel@nongnu.org; Wed, 26 Sep 2012 14:56:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TGwms-00076W-ND for qemu-devel@nongnu.org; Wed, 26 Sep 2012 14:56:52 -0400 Received: from 38.0.169.217.in-addr.arpa ([217.169.0.38]:43008 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGwms-00076K-H7 for qemu-devel@nongnu.org; Wed, 26 Sep 2012 14:56:46 -0400 From: Peter Maydell Date: Wed, 26 Sep 2012 19:48:53 +0100 Message-Id: <1348685335-16770-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 0/2] tcg/arm: Implement movcond_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Aurelien Jarno , Richard Henderson These patches implement movcond_i32 for the ARM TCG backend; we emit "mov dst, v2; cmp c1, c2; movcc dst, v1". We could have done this with a pair of conditional movs, but (a) this is not actually any shorter (b) it means we don't get the common TCG code doing the work of avoiding "mov reg to itself" (c) conditional moves aren't quite as free as they used to be on the ARM7. (Tested using Aurelien's movcond-shift patches on the ARM frontend as something that will generate enough movconds.) Peter Maydell (2): tcg/arm: Factor out code to emit immediate or reg-reg op tcg/arm: Implement movcond_i32 tcg/arm/tcg-target.c | 56 +++++++++++++++++++++++++++----------------------- tcg/arm/tcg-target.h | 2 +- 2 files changed, 31 insertions(+), 27 deletions(-) -- 1.7.9.5