From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33691) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3KS-0000zB-Uy for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:55:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TH3KR-0005gN-Qf for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:55:52 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:50416) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3KR-0005ej-K0 for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:55:51 -0400 Received: by pbbrp2 with SMTP id rp2so2797089pbb.4 for ; Wed, 26 Sep 2012 18:55:50 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 26 Sep 2012 18:55:30 -0700 Message-Id: <1348710942-3040-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl All of this based on testing alpha-softmmu on sparcv8plus and sparcv9. There were 5 problems with sparcv8plus implementing 64-bit opcodes. This patch set is based on the "TCGCond improvments" patch set I've previously posted, primarily for its is_unsigned_cond and tcg_high_cond functions. (http://patchwork.ozlabs.org/patch/186567/) r~ Richard Henderson (12): tcg-sparc: Fix brcond2 tcg-sparc: Implement movcond. tcg-sparc: Fix setcond2 tcg-sparc: Fix qemu_st for 32-bit tcg-sparc: Fix setcond tcg-sparc: Fix add2/sub2 tcg-sparc: Use Z constraint for %g0 tcg-sparc: Optimize setcond2 equality compare with 0. tcg-sparc: Drop use of Bicc in favor of BPcc tcg-sparc: Dump illegal opode contents tcg-sparc: Emit BPr insns for brcond_i64 tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64 sparc-dis.c | 2 +- tcg/sparc/tcg-target.c | 643 ++++++++++++++++++++++++++++--------------------- tcg/sparc/tcg-target.h | 9 +- 3 files changed, 381 insertions(+), 273 deletions(-) -- 1.7.11.4