From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>
Subject: [Qemu-devel] [PATCH 05/12] tcg-sparc: Fix setcond
Date: Wed, 26 Sep 2012 18:55:35 -0700 [thread overview]
Message-ID: <1348710942-3040-6-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1348710942-3040-1-git-send-email-rth@twiddle.net>
The set of comparisons that can immediately use the carry are LTU/GEU,
not LTU/LEU. Don't swap operands when we need a temp register; the
register may already be in use from setcond2.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index e55b792..c3e15b9 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -617,32 +617,37 @@ static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const)
{
- TCGArg t;
-
/* For 32-bit comparisons, we can play games with ADDX/SUBX. */
switch (cond) {
+ case TCG_COND_LTU:
+ case TCG_COND_GEU:
+ /* The result of the comparison is in the carry bit. */
+ break;
+
case TCG_COND_EQ:
case TCG_COND_NE:
+ /* For equality, we can transform to inequality vs zero. */
if (c2 != 0) {
tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
}
c1 = TCG_REG_G0, c2 = ret, c2const = 0;
- cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
+ cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
break;
case TCG_COND_GTU:
- case TCG_COND_GEU:
- if (c2const && c2 != 0) {
- tcg_out_movi_imm13(s, TCG_REG_T1, c2);
- c2 = TCG_REG_T1;
- }
- t = c1, c1 = c2, c2 = t, c2const = 0;
- cond = tcg_swap_cond(cond);
- break;
-
- case TCG_COND_LTU:
case TCG_COND_LEU:
- break;
+ /* If we don't need to load a constant into a register, we can
+ swap the operands on GTU/LEU. There's no benefit to loading
+ the constant into a temporary register. */
+ if (!c2const || c2 == 0) {
+ TCGArg t = c1;
+ c1 = c2;
+ c2 = t;
+ c2const = 0;
+ cond = tcg_swap_cond(cond);
+ break;
+ }
+ /* FALLTHRU */
default:
tcg_out_cmp(s, c1, c2, c2const);
--
1.7.11.4
next prev parent reply other threads:[~2012-09-27 1:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 01/12] tcg-sparc: Fix brcond2 Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 02/12] tcg-sparc: Implement movcond Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 03/12] tcg-sparc: Fix setcond2 Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 04/12] tcg-sparc: Fix qemu_st for 32-bit Richard Henderson
2012-09-27 1:55 ` Richard Henderson [this message]
2012-09-27 1:55 ` [Qemu-devel] [PATCH 06/12] tcg-sparc: Fix add2/sub2 Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 07/12] tcg-sparc: Use Z constraint for %g0 Richard Henderson
2012-09-29 11:55 ` Blue Swirl
2012-09-27 1:55 ` [Qemu-devel] [PATCH 08/12] tcg-sparc: Optimize setcond2 equality compare with 0 Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 09/12] tcg-sparc: Drop use of Bicc in favor of BPcc Richard Henderson
2012-09-29 12:07 ` Blue Swirl
2012-09-29 17:21 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 10/12] tcg-sparc: Dump illegal opode contents Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 11/12] tcg-sparc: Emit BPr insns for brcond_i64 Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 12/12] tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64 Richard Henderson
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