* [Qemu-devel] [PATCH 01/12] tcg-sparc: Fix brcond2
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 02/12] tcg-sparc: Implement movcond Richard Henderson
` (10 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Much the same problem as recently fixed for hppa.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 23 +++++++----------------
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index bb43e83..726fb9b 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -561,33 +561,24 @@ static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
/* Note that we fill one of the delay slots with the second compare. */
switch (cond) {
case TCG_COND_EQ:
- cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
- tcg_out_branch_i32(s, cc, label_next);
+ tcg_out_branch_i32(s, COND_NE, label_next);
tcg_out_cmp(s, al, bl, blconst);
- cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
- tcg_out_branch_i32(s, cc, label_dest);
+ tcg_out_branch_i32(s, COND_E, label_dest);
break;
case TCG_COND_NE:
- cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
- tcg_out_branch_i32(s, cc, label_dest);
+ tcg_out_branch_i32(s, COND_NE, label_dest);
tcg_out_cmp(s, al, bl, blconst);
- tcg_out_branch_i32(s, cc, label_dest);
+ tcg_out_branch_i32(s, COND_NE, label_dest);
break;
default:
- /* ??? One could fairly easily special-case 64-bit unsigned
- compares against 32-bit zero-extended constants. For instance,
- we know that (unsigned)AH < 0 is false and need not emit it.
- Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
- second branch will never be taken. */
- cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
+ cc = tcg_cond_to_bcond[tcg_high_cond(cond)];
tcg_out_branch_i32(s, cc, label_dest);
tcg_out_nop(s);
- cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
- tcg_out_branch_i32(s, cc, label_next);
+ tcg_out_branch_i32(s, COND_NE, label_next);
tcg_out_cmp(s, al, bl, blconst);
- cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
+ cc = tcg_cond_to_bcond[tcg_unsigned_cond(cond)];
tcg_out_branch_i32(s, cc, label_dest);
break;
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 02/12] tcg-sparc: Implement movcond.
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 01/12] tcg-sparc: Fix brcond2 Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 03/12] tcg-sparc: Fix setcond2 Richard Henderson
` (9 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 43 ++++++++++++++++++++++++++++++++++++-------
tcg/sparc/tcg-target.h | 4 ++--
2 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 726fb9b..c10e3b1 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -539,6 +539,22 @@ static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
tcg_out_nop(s);
}
+static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGArg ret,
+ TCGArg v1, int v1const)
+{
+ tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
+ | INSN_RS1(tcg_cond_to_bcond[cond])
+ | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
+}
+
+static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
+ TCGArg c1, TCGArg c2, int c2const,
+ TCGArg v1, int v1const)
+{
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
+}
+
#if TCG_TARGET_REG_BITS == 64
static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2,
@@ -548,6 +564,14 @@ static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
tcg_out_nop(s);
}
+
+static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
+ TCGArg c1, TCGArg c2, int c2const,
+ TCGArg v1, int v1const)
+{
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
+}
#else
static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
TCGArg al, TCGArg ah,
@@ -621,9 +645,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
default:
tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movi_imm13(s, ret, 0);
- tcg_out32(s, ARITH_MOVCC | INSN_RD(ret)
- | INSN_RS1(tcg_cond_to_bcond[cond])
- | MOVCC_ICC | INSN_IMM11(1));
+ tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
return;
}
@@ -641,9 +663,7 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
{
tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movi_imm13(s, ret, 0);
- tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
- | INSN_RS1(tcg_cond_to_bcond[cond])
- | MOVCC_XCC | INSN_IMM11(1));
+ tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
}
#else
static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
@@ -1203,6 +1223,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_setcond_i32(s, args[3], args[0], args[1],
args[2], const_args[2]);
break;
+ case INDEX_op_movcond_i32:
+ tcg_out_movcond_i32(s, args[5], args[0], args[1],
+ args[2], const_args[2], args[3], const_args[3]);
+ break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
@@ -1338,7 +1362,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_setcond_i64(s, args[3], args[0], args[1],
args[2], const_args[2]);
break;
-
+ case INDEX_op_movcond_i64:
+ tcg_out_movcond_i64(s, args[5], args[0], args[1],
+ args[2], const_args[2], args[3], const_args[3]);
+ break;
#endif
gen_arith:
tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
@@ -1394,6 +1421,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_brcond_i32, { "r", "rJ" } },
{ INDEX_op_setcond_i32, { "r", "r", "rJ" } },
+ { INDEX_op_movcond_i32, { "r", "r", "rJ", "rI", "0" } },
#if TCG_TARGET_REG_BITS == 32
{ INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
@@ -1443,6 +1471,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_brcond_i64, { "r", "rJ" } },
{ INDEX_op_setcond_i64, { "r", "r", "rJ" } },
+ { INDEX_op_movcond_i64, { "r", "r", "rJ", "rI", "0" } },
#endif
#if TCG_TARGET_REG_BITS == 64
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 6314ffb..c718a52 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -99,7 +99,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64 1
@@ -121,7 +121,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_movcond_i64 0
+#define TCG_TARGET_HAS_movcond_i64 1
#endif
#define TCG_TARGET_HAS_GUEST_BASE
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 03/12] tcg-sparc: Fix setcond2
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 01/12] tcg-sparc: Fix brcond2 Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 02/12] tcg-sparc: Implement movcond Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 04/12] tcg-sparc: Fix qemu_st for 32-bit Richard Henderson
` (8 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Like brcond2, use tcg_high_cond. Use movcc instead of branches.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 38 ++++++++++++++++++--------------------
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index c10e3b1..9d4b11a 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -337,7 +337,9 @@ static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
static inline void tcg_out_mov(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg)
{
- tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
+ if (ret != arg) {
+ tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
+ }
}
static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
@@ -671,33 +673,29 @@ static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg bl, int blconst,
TCGArg bh, int bhconst)
{
- int lab;
+ int tmp = TCG_REG_T1;
+
+ /* Note that the low parts are fully consumed before tmp is set. */
+ if (ret != ah && (bhconst || ret != bh)) {
+ tmp = ret;
+ }
switch (cond) {
case TCG_COND_EQ:
- tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_T1, al, bl, blconst);
- tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
- tcg_out_arith(s, ret, ret, TCG_REG_T1, ARITH_AND);
- break;
-
case TCG_COND_NE:
- tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_T1, al, al, blconst);
- tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
- tcg_out_arith(s, ret, ret, TCG_REG_T1, ARITH_OR);
+ tcg_out_setcond_i32(s, cond, tmp, al, bl, blconst);
+ tcg_out_cmp(s, ah, bh, bhconst);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, tmp);
+ tcg_out_movcc(s, TCG_COND_NE, MOVCC_ICC, ret, cond == TCG_COND_NE, 1);
break;
default:
- lab = gen_new_label();
-
+ /* <= : ah < bh | (ah == bh && al <= bl) */
+ tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), tmp, al, bl, blconst);
tcg_out_cmp(s, ah, bh, bhconst);
- tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
- tcg_out_movi_imm13(s, ret, 1);
- tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
- tcg_out_movi_imm13(s, ret, 0);
-
- tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
-
- tcg_out_label(s, lab, s->code_ptr);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, tmp);
+ tcg_out_movcc(s, TCG_COND_NE, MOVCC_ICC, ret, 0, 1);
+ tcg_out_movcc(s, tcg_high_cond(cond), MOVCC_ICC, ret, 1, 1);
break;
}
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 04/12] tcg-sparc: Fix qemu_st for 32-bit
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (2 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 03/12] tcg-sparc: Fix setcond2 Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 05/12] tcg-sparc: Fix setcond Richard Henderson
` (7 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
The datalo variable is still live in the miss path. Use another
when reconstructing the full data value.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 9d4b11a..e55b792 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -985,7 +985,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
{
int addrlo_idx = 1, datalo, datahi, addr_reg;
#if defined(CONFIG_SOFTMMU)
- int memi_idx, memi, n;
+ int memi_idx, memi, n, datafull;
uint32_t *label_ptr;
#endif
@@ -1002,12 +1002,13 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
addr_reg = tcg_out_tlb_load(s, addrlo_idx, memi, sizeop, args,
offsetof(CPUTLBEntry, addr_write));
+ datafull = datalo;
if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
/* Reconstruct the full 64-bit value. */
tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL);
tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
tcg_out_arith(s, TCG_REG_O2, TCG_REG_T1, TCG_REG_O2, ARITH_OR);
- datalo = TCG_REG_O2;
+ datafull = TCG_REG_O2;
}
/* The fast path is exactly one insn. Thus we can perform the entire
@@ -1018,7 +1019,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
| ((TARGET_LONG_BITS == 64) << 21)
| (1 << 29) | (1 << 19)));
/* delay slot */
- tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_O1, qemu_st_opc[sizeop]);
+ tcg_out_ldst_rr(s, datafull, addr_reg, TCG_REG_O1, qemu_st_opc[sizeop]);
/* TLB Miss. */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 05/12] tcg-sparc: Fix setcond
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (3 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 04/12] tcg-sparc: Fix qemu_st for 32-bit Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 06/12] tcg-sparc: Fix add2/sub2 Richard Henderson
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
The set of comparisons that can immediately use the carry are LTU/GEU,
not LTU/LEU. Don't swap operands when we need a temp register; the
register may already be in use from setcond2.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index e55b792..c3e15b9 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -617,32 +617,37 @@ static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const)
{
- TCGArg t;
-
/* For 32-bit comparisons, we can play games with ADDX/SUBX. */
switch (cond) {
+ case TCG_COND_LTU:
+ case TCG_COND_GEU:
+ /* The result of the comparison is in the carry bit. */
+ break;
+
case TCG_COND_EQ:
case TCG_COND_NE:
+ /* For equality, we can transform to inequality vs zero. */
if (c2 != 0) {
tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
}
c1 = TCG_REG_G0, c2 = ret, c2const = 0;
- cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
+ cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
break;
case TCG_COND_GTU:
- case TCG_COND_GEU:
- if (c2const && c2 != 0) {
- tcg_out_movi_imm13(s, TCG_REG_T1, c2);
- c2 = TCG_REG_T1;
- }
- t = c1, c1 = c2, c2 = t, c2const = 0;
- cond = tcg_swap_cond(cond);
- break;
-
- case TCG_COND_LTU:
case TCG_COND_LEU:
- break;
+ /* If we don't need to load a constant into a register, we can
+ swap the operands on GTU/LEU. There's no benefit to loading
+ the constant into a temporary register. */
+ if (!c2const || c2 == 0) {
+ TCGArg t = c1;
+ c1 = c2;
+ c2 = t;
+ c2const = 0;
+ cond = tcg_swap_cond(cond);
+ break;
+ }
+ /* FALLTHRU */
default:
tcg_out_cmp(s, c1, c2, c2const);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 06/12] tcg-sparc: Fix add2/sub2
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (4 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 05/12] tcg-sparc: Fix setcond Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 07/12] tcg-sparc: Use Z constraint for %g0 Richard Henderson
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
We must care not to clobber the high parts before we consume them.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 30 ++++++++++++++++++++++--------
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index c3e15b9..3154992 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -704,6 +704,22 @@ static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
break;
}
}
+
+static void tcg_out_addsub2(TCGContext *s, TCGArg rl, TCGArg rh,
+ TCGArg al, TCGArg ah, TCGArg bl, int blconst,
+ TCGArg bh, int bhconst, int opl, int oph)
+{
+ TCGArg tmp = TCG_REG_T1;
+
+ /* Note that the low parts are fully consumed before tmp is set. */
+ if (rl != ah && (bhconst || rl != bh)) {
+ tmp = rl;
+ }
+
+ tcg_out_arithc(s, tmp, al, bl, blconst, opl);
+ tcg_out_arithc(s, rh, ah, bh, bhconst, oph);
+ tcg_out_mov(s, TCG_TYPE_I32, rl, tmp);
+}
#endif
/* Generate global QEMU prologue and epilogue code */
@@ -1244,16 +1260,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
args[4], const_args[4]);
break;
case INDEX_op_add2_i32:
- tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
- ARITH_ADDCC);
- tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
- ARITH_ADDX);
+ tcg_out_addsub2(s, args[0], args[1], args[2], args[3],
+ args[4], const_args[4], args[5], const_args[5],
+ ARITH_ADDCC, ARITH_ADDX);
break;
case INDEX_op_sub2_i32:
- tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
- ARITH_SUBCC);
- tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
- ARITH_SUBX);
+ tcg_out_addsub2(s, args[0], args[1], args[2], args[3],
+ args[4], const_args[4], args[5], const_args[5],
+ ARITH_SUBCC, ARITH_SUBX);
break;
case INDEX_op_mulu2_i32:
tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 07/12] tcg-sparc: Use Z constraint for %g0
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (5 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 06/12] tcg-sparc: Fix add2/sub2 Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-29 11:55 ` Blue Swirl
2012-09-27 1:55 ` [Qemu-devel] [PATCH 08/12] tcg-sparc: Optimize setcond2 equality compare with 0 Richard Henderson
` (4 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 109 ++++++++++++++++++++++++++-----------------------
tcg/sparc/tcg-target.h | 5 ++-
2 files changed, 60 insertions(+), 54 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 3154992..b1f3eaf 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -180,6 +180,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
case 'J':
ct->ct |= TCG_CT_CONST_S13;
break;
+ case 'Z':
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
default:
return -1;
}
@@ -197,6 +200,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
ct = arg_ct->ct;
if (ct & TCG_CT_CONST)
return 1;
+ else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
+ return 1;
else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
return 1;
else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
@@ -1413,40 +1418,40 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_ld16u_i32, { "r", "r" } },
{ INDEX_op_ld16s_i32, { "r", "r" } },
{ INDEX_op_ld_i32, { "r", "r" } },
- { INDEX_op_st8_i32, { "r", "r" } },
- { INDEX_op_st16_i32, { "r", "r" } },
- { INDEX_op_st_i32, { "r", "r" } },
-
- { INDEX_op_add_i32, { "r", "r", "rJ" } },
- { INDEX_op_mul_i32, { "r", "r", "rJ" } },
- { INDEX_op_div_i32, { "r", "r", "rJ" } },
- { INDEX_op_divu_i32, { "r", "r", "rJ" } },
- { INDEX_op_rem_i32, { "r", "r", "rJ" } },
- { INDEX_op_remu_i32, { "r", "r", "rJ" } },
- { INDEX_op_sub_i32, { "r", "r", "rJ" } },
- { INDEX_op_and_i32, { "r", "r", "rJ" } },
- { INDEX_op_andc_i32, { "r", "r", "rJ" } },
- { INDEX_op_or_i32, { "r", "r", "rJ" } },
- { INDEX_op_orc_i32, { "r", "r", "rJ" } },
- { INDEX_op_xor_i32, { "r", "r", "rJ" } },
-
- { INDEX_op_shl_i32, { "r", "r", "rJ" } },
- { INDEX_op_shr_i32, { "r", "r", "rJ" } },
- { INDEX_op_sar_i32, { "r", "r", "rJ" } },
+ { INDEX_op_st8_i32, { "rZ", "r" } },
+ { INDEX_op_st16_i32, { "rZ", "r" } },
+ { INDEX_op_st_i32, { "rZ", "r" } },
+
+ { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_mul_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_div_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_divu_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_rem_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_remu_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_and_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_andc_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_or_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_orc_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_xor_i32, { "r", "rZ", "rJ" } },
+
+ { INDEX_op_shl_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_shr_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_sar_i32, { "r", "rZ", "rJ" } },
{ INDEX_op_neg_i32, { "r", "rJ" } },
{ INDEX_op_not_i32, { "r", "rJ" } },
- { INDEX_op_brcond_i32, { "r", "rJ" } },
- { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
- { INDEX_op_movcond_i32, { "r", "r", "rJ", "rI", "0" } },
+ { INDEX_op_brcond_i32, { "rZ", "rJ" } },
+ { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } },
#if TCG_TARGET_REG_BITS == 32
- { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
- { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
- { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
- { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
- { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
+ { INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } },
+ { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rJ", "rJ" } },
+ { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
+ { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
+ { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
#endif
#if TCG_TARGET_REG_BITS == 64
@@ -1459,27 +1464,27 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_ld32u_i64, { "r", "r" } },
{ INDEX_op_ld32s_i64, { "r", "r" } },
{ INDEX_op_ld_i64, { "r", "r" } },
- { INDEX_op_st8_i64, { "r", "r" } },
- { INDEX_op_st16_i64, { "r", "r" } },
- { INDEX_op_st32_i64, { "r", "r" } },
- { INDEX_op_st_i64, { "r", "r" } },
-
- { INDEX_op_add_i64, { "r", "r", "rJ" } },
- { INDEX_op_mul_i64, { "r", "r", "rJ" } },
- { INDEX_op_div_i64, { "r", "r", "rJ" } },
- { INDEX_op_divu_i64, { "r", "r", "rJ" } },
- { INDEX_op_rem_i64, { "r", "r", "rJ" } },
- { INDEX_op_remu_i64, { "r", "r", "rJ" } },
- { INDEX_op_sub_i64, { "r", "r", "rJ" } },
- { INDEX_op_and_i64, { "r", "r", "rJ" } },
- { INDEX_op_andc_i64, { "r", "r", "rJ" } },
- { INDEX_op_or_i64, { "r", "r", "rJ" } },
- { INDEX_op_orc_i64, { "r", "r", "rJ" } },
- { INDEX_op_xor_i64, { "r", "r", "rJ" } },
-
- { INDEX_op_shl_i64, { "r", "r", "rJ" } },
- { INDEX_op_shr_i64, { "r", "r", "rJ" } },
- { INDEX_op_sar_i64, { "r", "r", "rJ" } },
+ { INDEX_op_st8_i64, { "rZ", "r" } },
+ { INDEX_op_st16_i64, { "rZ", "r" } },
+ { INDEX_op_st32_i64, { "rZ", "r" } },
+ { INDEX_op_st_i64, { "rZ", "r" } },
+
+ { INDEX_op_add_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_mul_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_div_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_divu_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_rem_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_remu_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_sub_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_and_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_andc_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_or_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_orc_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_xor_i64, { "r", "rZ", "rJ" } },
+
+ { INDEX_op_shl_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_shr_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_sar_i64, { "r", "rZ", "rJ" } },
{ INDEX_op_neg_i64, { "r", "rJ" } },
{ INDEX_op_not_i64, { "r", "rJ" } },
@@ -1487,9 +1492,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_ext32s_i64, { "r", "ri" } },
{ INDEX_op_ext32u_i64, { "r", "ri" } },
- { INDEX_op_brcond_i64, { "r", "rJ" } },
- { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
- { INDEX_op_movcond_i64, { "r", "r", "rJ", "rI", "0" } },
+ { INDEX_op_brcond_i64, { "rZ", "rJ" } },
+ { INDEX_op_setcond_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_movcond_i64, { "r", "rZ", "rJ", "rI", "0" } },
#endif
#if TCG_TARGET_REG_BITS == 64
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index c718a52..c2fbb23 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -62,8 +62,9 @@ typedef enum {
TCG_REG_I7,
} TCGReg;
-#define TCG_CT_CONST_S11 0x100
-#define TCG_CT_CONST_S13 0x200
+#define TCG_CT_CONST_S11 0x100
+#define TCG_CT_CONST_S13 0x200
+#define TCG_CT_CONST_ZERO 0x400
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_O6
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH 07/12] tcg-sparc: Use Z constraint for %g0
2012-09-27 1:55 ` [Qemu-devel] [PATCH 07/12] tcg-sparc: Use Z constraint for %g0 Richard Henderson
@ 2012-09-29 11:55 ` Blue Swirl
0 siblings, 0 replies; 16+ messages in thread
From: Blue Swirl @ 2012-09-29 11:55 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, Sep 27, 2012 at 1:55 AM, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/sparc/tcg-target.c | 109 ++++++++++++++++++++++++++-----------------------
> tcg/sparc/tcg-target.h | 5 ++-
> 2 files changed, 60 insertions(+), 54 deletions(-)
>
> diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
> index 3154992..b1f3eaf 100644
> --- a/tcg/sparc/tcg-target.c
> +++ b/tcg/sparc/tcg-target.c
> @@ -180,6 +180,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> case 'J':
> ct->ct |= TCG_CT_CONST_S13;
> break;
> + case 'Z':
> + ct->ct |= TCG_CT_CONST_ZERO;
> + break;
> default:
> return -1;
> }
> @@ -197,6 +200,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
> ct = arg_ct->ct;
> if (ct & TCG_CT_CONST)
> return 1;
> + else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
Please add braces.
> + return 1;
> else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
> return 1;
> else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
> @@ -1413,40 +1418,40 @@ static const TCGTargetOpDef sparc_op_defs[] = {
> { INDEX_op_ld16u_i32, { "r", "r" } },
> { INDEX_op_ld16s_i32, { "r", "r" } },
> { INDEX_op_ld_i32, { "r", "r" } },
> - { INDEX_op_st8_i32, { "r", "r" } },
> - { INDEX_op_st16_i32, { "r", "r" } },
> - { INDEX_op_st_i32, { "r", "r" } },
> -
> - { INDEX_op_add_i32, { "r", "r", "rJ" } },
> - { INDEX_op_mul_i32, { "r", "r", "rJ" } },
> - { INDEX_op_div_i32, { "r", "r", "rJ" } },
> - { INDEX_op_divu_i32, { "r", "r", "rJ" } },
> - { INDEX_op_rem_i32, { "r", "r", "rJ" } },
> - { INDEX_op_remu_i32, { "r", "r", "rJ" } },
> - { INDEX_op_sub_i32, { "r", "r", "rJ" } },
> - { INDEX_op_and_i32, { "r", "r", "rJ" } },
> - { INDEX_op_andc_i32, { "r", "r", "rJ" } },
> - { INDEX_op_or_i32, { "r", "r", "rJ" } },
> - { INDEX_op_orc_i32, { "r", "r", "rJ" } },
> - { INDEX_op_xor_i32, { "r", "r", "rJ" } },
> -
> - { INDEX_op_shl_i32, { "r", "r", "rJ" } },
> - { INDEX_op_shr_i32, { "r", "r", "rJ" } },
> - { INDEX_op_sar_i32, { "r", "r", "rJ" } },
> + { INDEX_op_st8_i32, { "rZ", "r" } },
> + { INDEX_op_st16_i32, { "rZ", "r" } },
> + { INDEX_op_st_i32, { "rZ", "r" } },
> +
> + { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_mul_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_div_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_divu_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_rem_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_remu_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_and_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_andc_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_or_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_orc_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_xor_i32, { "r", "rZ", "rJ" } },
> +
> + { INDEX_op_shl_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_shr_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_sar_i32, { "r", "rZ", "rJ" } },
>
> { INDEX_op_neg_i32, { "r", "rJ" } },
> { INDEX_op_not_i32, { "r", "rJ" } },
>
> - { INDEX_op_brcond_i32, { "r", "rJ" } },
> - { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
> - { INDEX_op_movcond_i32, { "r", "r", "rJ", "rI", "0" } },
> + { INDEX_op_brcond_i32, { "rZ", "rJ" } },
> + { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } },
> + { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } },
>
> #if TCG_TARGET_REG_BITS == 32
> - { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
> - { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
> - { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
> - { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
> - { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
> + { INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } },
> + { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rJ", "rJ" } },
> + { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
> + { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
> + { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
> #endif
>
> #if TCG_TARGET_REG_BITS == 64
> @@ -1459,27 +1464,27 @@ static const TCGTargetOpDef sparc_op_defs[] = {
> { INDEX_op_ld32u_i64, { "r", "r" } },
> { INDEX_op_ld32s_i64, { "r", "r" } },
> { INDEX_op_ld_i64, { "r", "r" } },
> - { INDEX_op_st8_i64, { "r", "r" } },
> - { INDEX_op_st16_i64, { "r", "r" } },
> - { INDEX_op_st32_i64, { "r", "r" } },
> - { INDEX_op_st_i64, { "r", "r" } },
> -
> - { INDEX_op_add_i64, { "r", "r", "rJ" } },
> - { INDEX_op_mul_i64, { "r", "r", "rJ" } },
> - { INDEX_op_div_i64, { "r", "r", "rJ" } },
> - { INDEX_op_divu_i64, { "r", "r", "rJ" } },
> - { INDEX_op_rem_i64, { "r", "r", "rJ" } },
> - { INDEX_op_remu_i64, { "r", "r", "rJ" } },
> - { INDEX_op_sub_i64, { "r", "r", "rJ" } },
> - { INDEX_op_and_i64, { "r", "r", "rJ" } },
> - { INDEX_op_andc_i64, { "r", "r", "rJ" } },
> - { INDEX_op_or_i64, { "r", "r", "rJ" } },
> - { INDEX_op_orc_i64, { "r", "r", "rJ" } },
> - { INDEX_op_xor_i64, { "r", "r", "rJ" } },
> -
> - { INDEX_op_shl_i64, { "r", "r", "rJ" } },
> - { INDEX_op_shr_i64, { "r", "r", "rJ" } },
> - { INDEX_op_sar_i64, { "r", "r", "rJ" } },
> + { INDEX_op_st8_i64, { "rZ", "r" } },
> + { INDEX_op_st16_i64, { "rZ", "r" } },
> + { INDEX_op_st32_i64, { "rZ", "r" } },
> + { INDEX_op_st_i64, { "rZ", "r" } },
> +
> + { INDEX_op_add_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_mul_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_div_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_divu_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_rem_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_remu_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_sub_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_and_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_andc_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_or_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_orc_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_xor_i64, { "r", "rZ", "rJ" } },
> +
> + { INDEX_op_shl_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_shr_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_sar_i64, { "r", "rZ", "rJ" } },
>
> { INDEX_op_neg_i64, { "r", "rJ" } },
> { INDEX_op_not_i64, { "r", "rJ" } },
> @@ -1487,9 +1492,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
> { INDEX_op_ext32s_i64, { "r", "ri" } },
> { INDEX_op_ext32u_i64, { "r", "ri" } },
>
> - { INDEX_op_brcond_i64, { "r", "rJ" } },
> - { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
> - { INDEX_op_movcond_i64, { "r", "r", "rJ", "rI", "0" } },
> + { INDEX_op_brcond_i64, { "rZ", "rJ" } },
> + { INDEX_op_setcond_i64, { "r", "rZ", "rJ" } },
> + { INDEX_op_movcond_i64, { "r", "rZ", "rJ", "rI", "0" } },
> #endif
>
> #if TCG_TARGET_REG_BITS == 64
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index c718a52..c2fbb23 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -62,8 +62,9 @@ typedef enum {
> TCG_REG_I7,
> } TCGReg;
>
> -#define TCG_CT_CONST_S11 0x100
> -#define TCG_CT_CONST_S13 0x200
> +#define TCG_CT_CONST_S11 0x100
> +#define TCG_CT_CONST_S13 0x200
> +#define TCG_CT_CONST_ZERO 0x400
>
> /* used for function call generation */
> #define TCG_REG_CALL_STACK TCG_REG_O6
> --
> 1.7.11.4
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 08/12] tcg-sparc: Optimize setcond2 equality compare with 0.
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (6 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 07/12] tcg-sparc: Use Z constraint for %g0 Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 09/12] tcg-sparc: Drop use of Bicc in favor of BPcc Richard Henderson
` (3 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index b1f3eaf..1618996 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -693,9 +693,18 @@ static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
switch (cond) {
case TCG_COND_EQ:
case TCG_COND_NE:
- tcg_out_setcond_i32(s, cond, tmp, al, bl, blconst);
- tcg_out_cmp(s, ah, bh, bhconst);
- tcg_out_mov(s, TCG_TYPE_I32, ret, tmp);
+ if (bl == 0 && bh == 0) {
+ if (cond == TCG_COND_EQ) {
+ tcg_out_arith(s, TCG_REG_G0, al, ah, ARITH_ORCC);
+ tcg_out_movi(s, TCG_TYPE_I32, ret, 1);
+ } else {
+ tcg_out_arith(s, ret, al, ah, ARITH_ORCC);
+ }
+ } else {
+ tcg_out_setcond_i32(s, cond, tmp, al, bl, blconst);
+ tcg_out_cmp(s, ah, bh, bhconst);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, tmp);
+ }
tcg_out_movcc(s, TCG_COND_NE, MOVCC_ICC, ret, cond == TCG_COND_NE, 1);
break;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 09/12] tcg-sparc: Drop use of Bicc in favor of BPcc
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (7 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 08/12] tcg-sparc: Optimize setcond2 equality compare with 0 Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-29 12:07 ` Blue Swirl
2012-09-27 1:55 ` [Qemu-devel] [PATCH 10/12] tcg-sparc: Dump illegal opode contents Richard Henderson
` (2 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Now that we're always sparcv9, we can not bother using Bicc for
32-bit branches and BPcc for 64-bit branches and instead always
use BPcc.
New interfaces allow less direct use of tcg_out32 and raw numbers
inside the qemu_ld/st routines.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 305 +++++++++++++++++++++++--------------------------
1 file changed, 145 insertions(+), 160 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 1618996..f3eb246 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -115,101 +115,6 @@ static const int tcg_target_call_oarg_regs[] = {
TCG_REG_O3,
};
-static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
-{
- return (val << ((sizeof(tcg_target_long) * 8 - bits))
- >> (sizeof(tcg_target_long) * 8 - bits)) == val;
-}
-
-static inline int check_fit_i32(uint32_t val, unsigned int bits)
-{
- return ((val << (32 - bits)) >> (32 - bits)) == val;
-}
-
-static void patch_reloc(uint8_t *code_ptr, int type,
- tcg_target_long value, tcg_target_long addend)
-{
- value += addend;
- switch (type) {
- case R_SPARC_32:
- if (value != (uint32_t)value)
- tcg_abort();
- *(uint32_t *)code_ptr = value;
- break;
- case R_SPARC_WDISP22:
- value -= (long)code_ptr;
- value >>= 2;
- if (!check_fit_tl(value, 22))
- tcg_abort();
- *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
- break;
- case R_SPARC_WDISP19:
- value -= (long)code_ptr;
- value >>= 2;
- if (!check_fit_tl(value, 19))
- tcg_abort();
- *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
- break;
- default:
- tcg_abort();
- }
-}
-
-/* parse target specific constraints */
-static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
-{
- const char *ct_str;
-
- ct_str = *pct_str;
- switch (ct_str[0]) {
- case 'r':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
- break;
- case 'L': /* qemu_ld/st constraint */
- ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
- // Helper args
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S11;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S13;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return -1;
- }
- ct_str++;
- *pct_str = ct_str;
- return 0;
-}
-
-/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val,
- const TCGArgConstraint *arg_ct)
-{
- int ct;
-
- ct = arg_ct->ct;
- if (ct & TCG_CT_CONST)
- return 1;
- else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
- return 1;
- else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
- return 1;
- else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
- return 1;
- else
- return 0;
-}
-
#define INSN_OP(x) ((x) << 30)
#define INSN_OP2(x) ((x) << 22)
#define INSN_OP3(x) ((x) << 19)
@@ -222,9 +127,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
-#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
+#define INSN_COND(x) ((x) << 25)
-#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
#define COND_N 0x0
#define COND_E 0x1
#define COND_LE 0x2
@@ -241,11 +145,17 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define COND_CC 0xd
#define COND_POS 0xe
#define COND_VC 0xf
-#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
+#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
#define MOVCC_ICC (1 << 18)
#define MOVCC_XCC (1 << 18 | 1 << 12)
+#define BPCC_ICC 0
+#define BPCC_XCC (2 << 20)
+#define BPCC_PT (1 << 19)
+#define BPCC_PN 0
+#define BPCC_A (1 << 29)
+
#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
@@ -318,6 +228,99 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
+static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
+{
+ return (val << ((sizeof(tcg_target_long) * 8 - bits))
+ >> (sizeof(tcg_target_long) * 8 - bits)) == val;
+}
+
+static inline int check_fit_i32(uint32_t val, unsigned int bits)
+{
+ return ((val << (32 - bits)) >> (32 - bits)) == val;
+}
+
+static void patch_reloc(uint8_t *code_ptr, int type,
+ tcg_target_long value, tcg_target_long addend)
+{
+ uint32_t insn;
+ value += addend;
+ switch (type) {
+ case R_SPARC_32:
+ if (value != (uint32_t)value) {
+ tcg_abort();
+ }
+ *(uint32_t *)code_ptr = value;
+ break;
+ case R_SPARC_WDISP19:
+ value -= (long)code_ptr;
+ if (!check_fit_tl(value >> 2, 19)) {
+ tcg_abort();
+ }
+ insn = *(uint32_t *)code_ptr;
+ insn &= ~INSN_OFF19(-1);
+ insn |= INSN_OFF19(value);
+ *(uint32_t *)code_ptr = insn;
+ break;
+ default:
+ tcg_abort();
+ }
+}
+
+/* parse target specific constraints */
+static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
+{
+ const char *ct_str;
+
+ ct_str = *pct_str;
+ switch (ct_str[0]) {
+ case 'r':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
+ break;
+ case 'L': /* qemu_ld/st constraint */
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
+ // Helper args
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
+ break;
+ case 'I':
+ ct->ct |= TCG_CT_CONST_S11;
+ break;
+ case 'J':
+ ct->ct |= TCG_CT_CONST_S13;
+ break;
+ case 'Z':
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+ default:
+ return -1;
+ }
+ ct_str++;
+ *pct_str = ct_str;
+ return 0;
+}
+
+/* test if a constant matches the constraint */
+static inline int tcg_target_const_match(tcg_target_long val,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct;
+
+ ct = arg_ct->ct;
+ if (ct & TCG_CT_CONST)
+ return 1;
+ else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
+ return 1;
+ else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
+ return 1;
+ else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
+ return 1;
+ else
+ return 0;
+}
+
static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
int op)
{
@@ -486,39 +489,6 @@ static inline void tcg_out_nop(TCGContext *s)
tcg_out_sethi(s, TCG_REG_G0, 0);
}
-static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
-{
- TCGLabel *l = &s->labels[label_index];
- uint32_t off22;
-
- if (l->has_value) {
- off22 = INSN_OFF22(l->u.value - (unsigned long)s->code_ptr);
- } else {
- /* Make sure to preserve destinations during retranslation. */
- off22 = *(uint32_t *)s->code_ptr & INSN_OFF22(-1);
- tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
- }
- tcg_out32(s, INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | off22);
-}
-
-#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
-{
- TCGLabel *l = &s->labels[label_index];
- uint32_t off19;
-
- if (l->has_value) {
- off19 = INSN_OFF19(l->u.value - (unsigned long)s->code_ptr);
- } else {
- /* Make sure to preserve destinations during retranslation. */
- off19 = *(uint32_t *)s->code_ptr & INSN_OFF19(-1);
- tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
- }
- tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
- (0x5 << 19) | off19));
-}
-#endif
-
static const uint8_t tcg_cond_to_bcond[] = {
[TCG_COND_EQ] = COND_E,
[TCG_COND_NE] = COND_NE,
@@ -532,17 +502,36 @@ static const uint8_t tcg_cond_to_bcond[] = {
[TCG_COND_GTU] = COND_GU,
};
+static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
+{
+ tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
+}
+
+static void tcg_out_bpcc(TCGContext *s, int scond, int flags, int label)
+{
+ TCGLabel *l = &s->labels[label];
+ int off19;
+
+ if (l->has_value) {
+ off19 = INSN_OFF19(l->u.value - (unsigned long)s->code_ptr);
+ } else {
+ /* Make sure to preserve destinations during retranslation. */
+ off19 = *(uint32_t *)s->code_ptr & INSN_OFF19(-1);
+ tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label, 0);
+ }
+ tcg_out_bpcc0(s, scond, flags, off19);
+}
+
static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
{
tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
}
-static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- int label_index)
+static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGArg arg1,
+ TCGArg arg2, int const_arg2, int label)
{
tcg_out_cmp(s, arg1, arg2, const_arg2);
- tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
+ tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, label);
tcg_out_nop(s);
}
@@ -563,12 +552,11 @@ static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
}
#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- int label_index)
+static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGArg arg1,
+ TCGArg arg2, int const_arg2, int label)
{
tcg_out_cmp(s, arg1, arg2, const_arg2);
- tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
+ tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, label);
tcg_out_nop(s);
}
@@ -585,32 +573,32 @@ static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
TCGArg bl, int blconst,
TCGArg bh, int bhconst, int label_dest)
{
- int cc, label_next = gen_new_label();
+ int scond, label_next = gen_new_label();
tcg_out_cmp(s, ah, bh, bhconst);
/* Note that we fill one of the delay slots with the second compare. */
switch (cond) {
case TCG_COND_EQ:
- tcg_out_branch_i32(s, COND_NE, label_next);
+ tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_next);
tcg_out_cmp(s, al, bl, blconst);
- tcg_out_branch_i32(s, COND_E, label_dest);
+ tcg_out_bpcc(s, COND_E, BPCC_ICC | BPCC_PT, label_dest);
break;
case TCG_COND_NE:
- tcg_out_branch_i32(s, COND_NE, label_dest);
+ tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_dest);
tcg_out_cmp(s, al, bl, blconst);
- tcg_out_branch_i32(s, COND_NE, label_dest);
+ tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_dest);
break;
default:
- cc = tcg_cond_to_bcond[tcg_high_cond(cond)];
- tcg_out_branch_i32(s, cc, label_dest);
+ scond = tcg_cond_to_bcond[tcg_high_cond(cond)];
+ tcg_out_bpcc(s, scond, BPCC_ICC | BPCC_PT, label_dest);
tcg_out_nop(s);
- tcg_out_branch_i32(s, COND_NE, label_next);
+ tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_next);
tcg_out_cmp(s, al, bl, blconst);
- cc = tcg_cond_to_bcond[tcg_unsigned_cond(cond)];
- tcg_out_branch_i32(s, cc, label_dest);
+ scond = tcg_cond_to_bcond[tcg_unsigned_cond(cond)];
+ tcg_out_bpcc(s, scond, BPCC_ICC | BPCC_PT, label_dest);
break;
}
tcg_out_nop(s);
@@ -903,8 +891,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
/* bne,pn %[xi]cc, label0 */
label_ptr[0] = (uint32_t *)s->code_ptr;
- tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_NE, 0) | INSN_OP2(0x1)
- | ((TARGET_LONG_BITS == 64) << 21)));
+ tcg_out_bpcc0(s, COND_NE, BPCC_PN
+ | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
/* TLB Hit. */
/* Load all 64-bits into an O/G register. */
@@ -919,8 +907,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
/* b,a,pt label1 */
label_ptr[1] = (uint32_t *)s->code_ptr;
- tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x1)
- | (1 << 29) | (1 << 19)));
+ tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0);
} else {
/* The fast path is exactly one insn. Thus we can perform the
entire TLB Hit in the (annulled) delay slot of the branch
@@ -929,9 +916,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
/* beq,a,pt %[xi]cc, label0 */
label_ptr[0] = NULL;
label_ptr[1] = (uint32_t *)s->code_ptr;
- tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1)
- | ((TARGET_LONG_BITS == 64) << 21)
- | (1 << 29) | (1 << 19)));
+ tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
+ | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
/* delay slot */
tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_O1, qemu_ld_opc[sizeop]);
}
@@ -1050,9 +1036,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
/* beq,a,pt %[xi]cc, label0 */
label_ptr = (uint32_t *)s->code_ptr;
- tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1)
- | ((TARGET_LONG_BITS == 64) << 21)
- | (1 << 29) | (1 << 19)));
+ tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
+ | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
/* delay slot */
tcg_out_ldst_rr(s, datafull, addr_reg, TCG_REG_O1, qemu_st_opc[sizeop]);
@@ -1144,7 +1129,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_jmp:
case INDEX_op_br:
- tcg_out_branch_i32(s, COND_A, args[0]);
+ tcg_out_bpcc(s, COND_A, BPCC_PT, args[0]);
tcg_out_nop(s);
break;
case INDEX_op_movi_i32:
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH 09/12] tcg-sparc: Drop use of Bicc in favor of BPcc
2012-09-27 1:55 ` [Qemu-devel] [PATCH 09/12] tcg-sparc: Drop use of Bicc in favor of BPcc Richard Henderson
@ 2012-09-29 12:07 ` Blue Swirl
2012-09-29 17:21 ` Richard Henderson
0 siblings, 1 reply; 16+ messages in thread
From: Blue Swirl @ 2012-09-29 12:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, Sep 27, 2012 at 1:55 AM, Richard Henderson <rth@twiddle.net> wrote:
> Now that we're always sparcv9, we can not bother using Bicc for
> 32-bit branches and BPcc for 64-bit branches and instead always
> use BPcc.
But then the branch range is smaller (19 bits). The code buffer is
32M, wouldn't we use BPcc for TB linking too and then the range could
be exceed?
>
> New interfaces allow less direct use of tcg_out32 and raw numbers
> inside the qemu_ld/st routines.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/sparc/tcg-target.c | 305 +++++++++++++++++++++++--------------------------
> 1 file changed, 145 insertions(+), 160 deletions(-)
>
> diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
> index 1618996..f3eb246 100644
> --- a/tcg/sparc/tcg-target.c
> +++ b/tcg/sparc/tcg-target.c
> @@ -115,101 +115,6 @@ static const int tcg_target_call_oarg_regs[] = {
> TCG_REG_O3,
> };
>
> -static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
> -{
> - return (val << ((sizeof(tcg_target_long) * 8 - bits))
> - >> (sizeof(tcg_target_long) * 8 - bits)) == val;
> -}
> -
> -static inline int check_fit_i32(uint32_t val, unsigned int bits)
> -{
> - return ((val << (32 - bits)) >> (32 - bits)) == val;
> -}
> -
> -static void patch_reloc(uint8_t *code_ptr, int type,
> - tcg_target_long value, tcg_target_long addend)
> -{
> - value += addend;
> - switch (type) {
> - case R_SPARC_32:
> - if (value != (uint32_t)value)
> - tcg_abort();
> - *(uint32_t *)code_ptr = value;
> - break;
> - case R_SPARC_WDISP22:
> - value -= (long)code_ptr;
> - value >>= 2;
> - if (!check_fit_tl(value, 22))
> - tcg_abort();
> - *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
> - break;
> - case R_SPARC_WDISP19:
> - value -= (long)code_ptr;
> - value >>= 2;
> - if (!check_fit_tl(value, 19))
> - tcg_abort();
> - *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
> - break;
> - default:
> - tcg_abort();
> - }
> -}
> -
> -/* parse target specific constraints */
> -static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> -{
> - const char *ct_str;
> -
> - ct_str = *pct_str;
> - switch (ct_str[0]) {
> - case 'r':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
> - break;
> - case 'L': /* qemu_ld/st constraint */
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
> - // Helper args
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
> - break;
> - case 'I':
> - ct->ct |= TCG_CT_CONST_S11;
> - break;
> - case 'J':
> - ct->ct |= TCG_CT_CONST_S13;
> - break;
> - case 'Z':
> - ct->ct |= TCG_CT_CONST_ZERO;
> - break;
> - default:
> - return -1;
> - }
> - ct_str++;
> - *pct_str = ct_str;
> - return 0;
> -}
> -
> -/* test if a constant matches the constraint */
> -static inline int tcg_target_const_match(tcg_target_long val,
> - const TCGArgConstraint *arg_ct)
> -{
> - int ct;
> -
> - ct = arg_ct->ct;
> - if (ct & TCG_CT_CONST)
> - return 1;
> - else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
> - return 1;
> - else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
> - return 1;
> - else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
> - return 1;
> - else
> - return 0;
> -}
> -
> #define INSN_OP(x) ((x) << 30)
> #define INSN_OP2(x) ((x) << 22)
> #define INSN_OP3(x) ((x) << 19)
> @@ -222,9 +127,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
> #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
> #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
> #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
> -#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
> +#define INSN_COND(x) ((x) << 25)
>
> -#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
> #define COND_N 0x0
> #define COND_E 0x1
> #define COND_LE 0x2
> @@ -241,11 +145,17 @@ static inline int tcg_target_const_match(tcg_target_long val,
> #define COND_CC 0xd
> #define COND_POS 0xe
> #define COND_VC 0xf
> -#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
> +#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
>
> #define MOVCC_ICC (1 << 18)
> #define MOVCC_XCC (1 << 18 | 1 << 12)
>
> +#define BPCC_ICC 0
> +#define BPCC_XCC (2 << 20)
> +#define BPCC_PT (1 << 19)
> +#define BPCC_PN 0
> +#define BPCC_A (1 << 29)
> +
> #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
> #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
> #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
> @@ -318,6 +228,99 @@ static inline int tcg_target_const_match(tcg_target_long val,
> #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
> #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
>
> +static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
> +{
> + return (val << ((sizeof(tcg_target_long) * 8 - bits))
> + >> (sizeof(tcg_target_long) * 8 - bits)) == val;
> +}
> +
> +static inline int check_fit_i32(uint32_t val, unsigned int bits)
> +{
> + return ((val << (32 - bits)) >> (32 - bits)) == val;
> +}
> +
> +static void patch_reloc(uint8_t *code_ptr, int type,
> + tcg_target_long value, tcg_target_long addend)
> +{
> + uint32_t insn;
> + value += addend;
> + switch (type) {
> + case R_SPARC_32:
> + if (value != (uint32_t)value) {
> + tcg_abort();
> + }
> + *(uint32_t *)code_ptr = value;
> + break;
> + case R_SPARC_WDISP19:
> + value -= (long)code_ptr;
> + if (!check_fit_tl(value >> 2, 19)) {
> + tcg_abort();
> + }
> + insn = *(uint32_t *)code_ptr;
> + insn &= ~INSN_OFF19(-1);
> + insn |= INSN_OFF19(value);
> + *(uint32_t *)code_ptr = insn;
> + break;
> + default:
> + tcg_abort();
> + }
> +}
> +
> +/* parse target specific constraints */
> +static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> +{
> + const char *ct_str;
> +
> + ct_str = *pct_str;
> + switch (ct_str[0]) {
> + case 'r':
> + ct->ct |= TCG_CT_REG;
> + tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
> + break;
> + case 'L': /* qemu_ld/st constraint */
> + ct->ct |= TCG_CT_REG;
> + tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
> + // Helper args
Please use C89 comments.
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
> + break;
> + case 'I':
> + ct->ct |= TCG_CT_CONST_S11;
> + break;
> + case 'J':
> + ct->ct |= TCG_CT_CONST_S13;
> + break;
> + case 'Z':
> + ct->ct |= TCG_CT_CONST_ZERO;
> + break;
> + default:
> + return -1;
> + }
> + ct_str++;
> + *pct_str = ct_str;
> + return 0;
> +}
> +
> +/* test if a constant matches the constraint */
> +static inline int tcg_target_const_match(tcg_target_long val,
> + const TCGArgConstraint *arg_ct)
> +{
> + int ct;
> +
> + ct = arg_ct->ct;
> + if (ct & TCG_CT_CONST)
Please add braces.
> + return 1;
> + else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
> + return 1;
> + else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
> + return 1;
> + else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
> + return 1;
> + else
> + return 0;
> +}
> +
> static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
> int op)
> {
> @@ -486,39 +489,6 @@ static inline void tcg_out_nop(TCGContext *s)
> tcg_out_sethi(s, TCG_REG_G0, 0);
> }
>
> -static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
> -{
> - TCGLabel *l = &s->labels[label_index];
> - uint32_t off22;
> -
> - if (l->has_value) {
> - off22 = INSN_OFF22(l->u.value - (unsigned long)s->code_ptr);
> - } else {
> - /* Make sure to preserve destinations during retranslation. */
> - off22 = *(uint32_t *)s->code_ptr & INSN_OFF22(-1);
> - tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
> - }
> - tcg_out32(s, INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | off22);
> -}
> -
> -#if TCG_TARGET_REG_BITS == 64
> -static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
> -{
> - TCGLabel *l = &s->labels[label_index];
> - uint32_t off19;
> -
> - if (l->has_value) {
> - off19 = INSN_OFF19(l->u.value - (unsigned long)s->code_ptr);
> - } else {
> - /* Make sure to preserve destinations during retranslation. */
> - off19 = *(uint32_t *)s->code_ptr & INSN_OFF19(-1);
> - tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
> - }
> - tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
> - (0x5 << 19) | off19));
> -}
> -#endif
> -
> static const uint8_t tcg_cond_to_bcond[] = {
> [TCG_COND_EQ] = COND_E,
> [TCG_COND_NE] = COND_NE,
> @@ -532,17 +502,36 @@ static const uint8_t tcg_cond_to_bcond[] = {
> [TCG_COND_GTU] = COND_GU,
> };
>
> +static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
> +{
> + tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
> +}
> +
> +static void tcg_out_bpcc(TCGContext *s, int scond, int flags, int label)
> +{
> + TCGLabel *l = &s->labels[label];
> + int off19;
> +
> + if (l->has_value) {
> + off19 = INSN_OFF19(l->u.value - (unsigned long)s->code_ptr);
> + } else {
> + /* Make sure to preserve destinations during retranslation. */
> + off19 = *(uint32_t *)s->code_ptr & INSN_OFF19(-1);
> + tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label, 0);
> + }
> + tcg_out_bpcc0(s, scond, flags, off19);
> +}
> +
> static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
> {
> tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
> }
>
> -static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
> - TCGArg arg1, TCGArg arg2, int const_arg2,
> - int label_index)
> +static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGArg arg1,
> + TCGArg arg2, int const_arg2, int label)
> {
> tcg_out_cmp(s, arg1, arg2, const_arg2);
> - tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
> + tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, label);
> tcg_out_nop(s);
> }
>
> @@ -563,12 +552,11 @@ static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
> }
>
> #if TCG_TARGET_REG_BITS == 64
> -static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
> - TCGArg arg1, TCGArg arg2, int const_arg2,
> - int label_index)
> +static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGArg arg1,
> + TCGArg arg2, int const_arg2, int label)
> {
> tcg_out_cmp(s, arg1, arg2, const_arg2);
> - tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
> + tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, label);
> tcg_out_nop(s);
> }
>
> @@ -585,32 +573,32 @@ static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
> TCGArg bl, int blconst,
> TCGArg bh, int bhconst, int label_dest)
> {
> - int cc, label_next = gen_new_label();
> + int scond, label_next = gen_new_label();
>
> tcg_out_cmp(s, ah, bh, bhconst);
>
> /* Note that we fill one of the delay slots with the second compare. */
> switch (cond) {
> case TCG_COND_EQ:
> - tcg_out_branch_i32(s, COND_NE, label_next);
> + tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_next);
> tcg_out_cmp(s, al, bl, blconst);
> - tcg_out_branch_i32(s, COND_E, label_dest);
> + tcg_out_bpcc(s, COND_E, BPCC_ICC | BPCC_PT, label_dest);
> break;
>
> case TCG_COND_NE:
> - tcg_out_branch_i32(s, COND_NE, label_dest);
> + tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_dest);
> tcg_out_cmp(s, al, bl, blconst);
> - tcg_out_branch_i32(s, COND_NE, label_dest);
> + tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_dest);
> break;
>
> default:
> - cc = tcg_cond_to_bcond[tcg_high_cond(cond)];
> - tcg_out_branch_i32(s, cc, label_dest);
> + scond = tcg_cond_to_bcond[tcg_high_cond(cond)];
> + tcg_out_bpcc(s, scond, BPCC_ICC | BPCC_PT, label_dest);
> tcg_out_nop(s);
> - tcg_out_branch_i32(s, COND_NE, label_next);
> + tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_next);
> tcg_out_cmp(s, al, bl, blconst);
> - cc = tcg_cond_to_bcond[tcg_unsigned_cond(cond)];
> - tcg_out_branch_i32(s, cc, label_dest);
> + scond = tcg_cond_to_bcond[tcg_unsigned_cond(cond)];
> + tcg_out_bpcc(s, scond, BPCC_ICC | BPCC_PT, label_dest);
> break;
> }
> tcg_out_nop(s);
> @@ -903,8 +891,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
>
> /* bne,pn %[xi]cc, label0 */
> label_ptr[0] = (uint32_t *)s->code_ptr;
> - tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_NE, 0) | INSN_OP2(0x1)
> - | ((TARGET_LONG_BITS == 64) << 21)));
> + tcg_out_bpcc0(s, COND_NE, BPCC_PN
> + | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
>
> /* TLB Hit. */
> /* Load all 64-bits into an O/G register. */
> @@ -919,8 +907,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
>
> /* b,a,pt label1 */
> label_ptr[1] = (uint32_t *)s->code_ptr;
> - tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x1)
> - | (1 << 29) | (1 << 19)));
> + tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0);
> } else {
> /* The fast path is exactly one insn. Thus we can perform the
> entire TLB Hit in the (annulled) delay slot of the branch
> @@ -929,9 +916,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
> /* beq,a,pt %[xi]cc, label0 */
> label_ptr[0] = NULL;
> label_ptr[1] = (uint32_t *)s->code_ptr;
> - tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1)
> - | ((TARGET_LONG_BITS == 64) << 21)
> - | (1 << 29) | (1 << 19)));
> + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
> + | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
> /* delay slot */
> tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_O1, qemu_ld_opc[sizeop]);
> }
> @@ -1050,9 +1036,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
> TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
> /* beq,a,pt %[xi]cc, label0 */
> label_ptr = (uint32_t *)s->code_ptr;
> - tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1)
> - | ((TARGET_LONG_BITS == 64) << 21)
> - | (1 << 29) | (1 << 19)));
> + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
> + | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
> /* delay slot */
> tcg_out_ldst_rr(s, datafull, addr_reg, TCG_REG_O1, qemu_st_opc[sizeop]);
>
> @@ -1144,7 +1129,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> break;
> case INDEX_op_jmp:
> case INDEX_op_br:
> - tcg_out_branch_i32(s, COND_A, args[0]);
> + tcg_out_bpcc(s, COND_A, BPCC_PT, args[0]);
Here we could check if the range is OK and use Bicc otherwise.
> tcg_out_nop(s);
> break;
> case INDEX_op_movi_i32:
> --
> 1.7.11.4
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH 09/12] tcg-sparc: Drop use of Bicc in favor of BPcc
2012-09-29 12:07 ` Blue Swirl
@ 2012-09-29 17:21 ` Richard Henderson
0 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-29 17:21 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
On 2012-09-29 05:07, Blue Swirl wrote:
> On Thu, Sep 27, 2012 at 1:55 AM, Richard Henderson <rth@twiddle.net> wrote:
>> Now that we're always sparcv9, we can not bother using Bicc for
>> 32-bit branches and BPcc for 64-bit branches and instead always
>> use BPcc.
>
> But then the branch range is smaller (19 bits). The code buffer is
> 32M, wouldn't we use BPcc for TB linking too and then the range could
> be exceed?
We use CALL for TB linking, with its 30 bit range.
BPcc is only needed within a TB, which should never come close to 2MB.
r~
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 10/12] tcg-sparc: Dump illegal opode contents
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (8 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 09/12] tcg-sparc: Drop use of Bicc in favor of BPcc Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 11/12] tcg-sparc: Emit BPr insns for brcond_i64 Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 12/12] tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64 Richard Henderson
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
sparc-dis.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sparc-dis.c b/sparc-dis.c
index cdd337a..1d017fa 100644
--- a/sparc-dis.c
+++ b/sparc-dis.c
@@ -3270,6 +3270,6 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
}
info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
- (*info->fprintf_func) (stream, _("unknown"));
+ (*info->fprintf_func) (stream, ".long %#08lx", insn);
return sizeof (buffer);
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 11/12] tcg-sparc: Emit BPr insns for brcond_i64
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (9 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 10/12] tcg-sparc: Dump illegal opode contents Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
2012-09-27 1:55 ` [Qemu-devel] [PATCH 12/12] tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64 Richard Henderson
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index f3eb246..90a041e 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -126,6 +126,7 @@ static const int tcg_target_call_oarg_regs[] = {
#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
+#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
#define INSN_COND(x) ((x) << 25)
@@ -147,6 +148,13 @@ static const int tcg_target_call_oarg_regs[] = {
#define COND_VC 0xf
#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
+#define RCOND_Z 1
+#define RCOND_LEZ 2
+#define RCOND_LZ 3
+#define RCOND_NZ 5
+#define RCOND_GZ 6
+#define RCOND_GEZ 7
+
#define MOVCC_ICC (1 << 18)
#define MOVCC_XCC (1 << 18 | 1 << 12)
@@ -156,6 +164,8 @@ static const int tcg_target_call_oarg_regs[] = {
#define BPCC_PN 0
#define BPCC_A (1 << 29)
+#define BPR_PT BPCC_PT
+
#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
@@ -251,6 +261,16 @@ static void patch_reloc(uint8_t *code_ptr, int type,
}
*(uint32_t *)code_ptr = value;
break;
+ case R_SPARC_WDISP16:
+ value -= (long)code_ptr;
+ if (!check_fit_tl(value >> 2, 16)) {
+ tcg_abort();
+ }
+ insn = *(uint32_t *)code_ptr;
+ insn &= ~INSN_OFF16(-1);
+ insn |= INSN_OFF16(value);
+ *(uint32_t *)code_ptr = insn;
+ break;
case R_SPARC_WDISP19:
value -= (long)code_ptr;
if (!check_fit_tl(value >> 2, 19)) {
@@ -502,6 +522,15 @@ static const uint8_t tcg_cond_to_bcond[] = {
[TCG_COND_GTU] = COND_GU,
};
+static const uint8_t tcg_cond_to_rcond[] = {
+ [TCG_COND_EQ] = RCOND_Z,
+ [TCG_COND_NE] = RCOND_NZ,
+ [TCG_COND_LT] = RCOND_LZ,
+ [TCG_COND_GT] = RCOND_GZ,
+ [TCG_COND_LE] = RCOND_LEZ,
+ [TCG_COND_GE] = RCOND_GEZ
+};
+
static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
{
tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
@@ -555,8 +584,24 @@ static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGArg arg1,
TCGArg arg2, int const_arg2, int label)
{
- tcg_out_cmp(s, arg1, arg2, const_arg2);
- tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, label);
+ /* For 64-bit signed comparisons vs zero, we can avoid the compare. */
+ if (arg2 == 0 && !is_unsigned_cond(cond)) {
+ TCGLabel *l = &s->labels[label];
+ int off16;
+
+ if (l->has_value) {
+ off16 = INSN_OFF16(l->u.value - (unsigned long)s->code_ptr);
+ } else {
+ /* Make sure to preserve destinations during retranslation. */
+ off16 = *(uint32_t *)s->code_ptr & INSN_OFF16(-1);
+ tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, label, 0);
+ }
+ tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1)
+ | INSN_COND(tcg_cond_to_rcond[cond]) | off16);
+ } else {
+ tcg_out_cmp(s, arg1, arg2, const_arg2);
+ tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, label);
+ }
tcg_out_nop(s);
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 12/12] tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64
2012-09-27 1:55 [Qemu-devel] [PATCH 00/12] tcg-sparc fixes and improvements Richard Henderson
` (10 preceding siblings ...)
2012-09-27 1:55 ` [Qemu-devel] [PATCH 11/12] tcg-sparc: Emit BPr insns for brcond_i64 Richard Henderson
@ 2012-09-27 1:55 ` Richard Henderson
11 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2012-09-27 1:55 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.c | 35 ++++++++++++++++++++++++++++++-----
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 90a041e..72f07f9 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -124,6 +124,7 @@ static const int tcg_target_call_oarg_regs[] = {
#define INSN_RS2(x) (x)
#define INSN_ASI(x) ((x) << 5)
+#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
@@ -185,6 +186,7 @@ static const int tcg_target_call_oarg_regs[] = {
#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
+#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
@@ -572,6 +574,14 @@ static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGArg ret,
| (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
}
+static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGArg ret, TCGArg c1,
+ TCGArg v1, int v1const)
+{
+ tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1)
+ | (tcg_cond_to_rcond[cond] << 10)
+ | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1)));
+}
+
static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const,
TCGArg v1, int v1const)
@@ -609,8 +619,16 @@ static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const,
TCGArg v1, int v1const)
{
- tcg_out_cmp(s, c1, c2, c2const);
- tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
+ /* For 64-bit signed comparisons vs zero, we can avoid the compare.
+ Note that the immediate range is one bit smaller, so we must check
+ for that as well. */
+ if (c2 == 0 && !is_unsigned_cond(cond)
+ && (!v1const || check_fit_tl(v1, 10))) {
+ tcg_out_movr(s, cond, ret, c1, v1, v1const);
+ } else {
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
+ }
}
#else
static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
@@ -706,9 +724,16 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const)
{
- tcg_out_cmp(s, c1, c2, c2const);
- tcg_out_movi_imm13(s, ret, 0);
- tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
+ /* For 64-bit signed comparisons vs zero, we can avoid the compare
+ if the input does not overlap the output. */
+ if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out_movr(s, cond, ret, c1, 1, 1);
+ } else {
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
+ }
}
#else
static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
--
1.7.11.4
^ permalink raw reply related [flat|nested] 16+ messages in thread