* [Qemu-devel] [PATCH v3] qemu/xen: Add 64 bits big bar support on qemu
@ 2012-09-27 3:01 Xudong Hao
2012-09-27 10:06 ` Stefano Stabellini
0 siblings, 1 reply; 2+ messages in thread
From: Xudong Hao @ 2012-09-27 3:01 UTC (permalink / raw)
To: stefano.stabellini; +Cc: Xudong Hao, qemu-devel, xen-devel
v3 changes from v2:
- Refine code following by the qemu code style
- As suggestion by Stefano, cheanup code, add some code comment
v2 changes from v1:
- Rebase to qemu upstream from qemu-xen
Currently it is assumed PCI device BAR access < 4G memory. If there is such a
device whose BAR size is larger than 4G, it must access > 4G memory address.
This patch enable the 64bits big BAR support on qemu.
Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
---
hw/xen_pt.c | 7 +++++--
hw/xen_pt_config_init.c | 39 ++++++++++++++++++++++++++-------------
2 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/hw/xen_pt.c b/hw/xen_pt.c
index 307119a..838bcea 100644
--- a/hw/xen_pt.c
+++ b/hw/xen_pt.c
@@ -410,14 +410,17 @@ static int xen_pt_register_regions(XenPCIPassthroughState *s)
if (r->type & XEN_HOST_PCI_REGION_TYPE_PREFETCH) {
type |= PCI_BASE_ADDRESS_MEM_PREFETCH;
}
+ if (r->type & XEN_HOST_PCI_REGION_TYPE_MEM_64) {
+ type |= PCI_BASE_ADDRESS_MEM_TYPE_64;
+ }
}
memory_region_init_io(&s->bar[i], &ops, &s->dev,
"xen-pci-pt-bar", r->size);
pci_register_bar(&s->dev, i, type, &s->bar[i]);
- XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%08"PRIx64
- " base_addr=0x%08"PRIx64" type: %#x)\n",
+ XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%lx"PRIx64
+ " base_addr=0x%lx"PRIx64" type: %#x)\n",
i, r->size, r->base_addr, type);
}
diff --git a/hw/xen_pt_config_init.c b/hw/xen_pt_config_init.c
index e524a40..0a5f82c 100644
--- a/hw/xen_pt_config_init.c
+++ b/hw/xen_pt_config_init.c
@@ -342,6 +342,23 @@ static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
#define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
#define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
+static bool is_64bit_bar(PCIIORegion *r)
+{
+ return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
+}
+
+static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
+{
+ if (is_64bit_bar(r)) {
+ uint64_t size64;
+ size64 = (r + 1)->size;
+ size64 <<= 32;
+ size64 += r->size;
+ return size64;
+ }
+ return r->size;
+}
+
static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
XenPTRegInfo *reg)
{
@@ -366,7 +383,7 @@ static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
/* check unused BAR */
r = &d->io_regions[index];
- if (r->size == 0) {
+ if (!xen_pt_get_bar_size(r)) {
return XEN_PT_BAR_FLAG_UNUSED;
}
@@ -481,7 +498,12 @@ static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
switch (s->bases[index].bar_flag) {
case XEN_PT_BAR_FLAG_MEM:
bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
- bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
+ if (!r_size) {
+ /* low 32 bits mask for 64 bit bars */
+ bar_ro_mask = XEN_PT_BAR_ALLF;
+ } else {
+ bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
+ }
break;
case XEN_PT_BAR_FLAG_IO:
bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
@@ -489,7 +511,7 @@ static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
break;
case XEN_PT_BAR_FLAG_UPPER:
bar_emu_mask = XEN_PT_BAR_ALLF;
- bar_ro_mask = 0; /* all upper 32bit are R/W */
+ bar_ro_mask = r_size ? r_size - 1 : 0;
break;
default:
break;
@@ -501,22 +523,13 @@ static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
/* check whether we need to update the virtual region address or not */
switch (s->bases[index].bar_flag) {
+ case XEN_PT_BAR_FLAG_UPPER:
case XEN_PT_BAR_FLAG_MEM:
/* nothing to do */
break;
case XEN_PT_BAR_FLAG_IO:
/* nothing to do */
break;
- case XEN_PT_BAR_FLAG_UPPER:
- if (cfg_entry->data) {
- if (cfg_entry->data != (XEN_PT_BAR_ALLF & ~bar_ro_mask)) {
- XEN_PT_WARN(d, "Guest attempt to set high MMIO Base Address. "
- "Ignore mapping. "
- "(offset: 0x%02x, high address: 0x%08x)\n",
- reg->offset, cfg_entry->data);
- }
- }
- break;
default:
break;
}
--
1.5.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH v3] qemu/xen: Add 64 bits big bar support on qemu
2012-09-27 3:01 [Qemu-devel] [PATCH v3] qemu/xen: Add 64 bits big bar support on qemu Xudong Hao
@ 2012-09-27 10:06 ` Stefano Stabellini
0 siblings, 0 replies; 2+ messages in thread
From: Stefano Stabellini @ 2012-09-27 10:06 UTC (permalink / raw)
To: Xudong Hao
Cc: xen-devel@lists.xen.org, qemu-devel@nongnu.org,
Stefano Stabellini
On Thu, 27 Sep 2012, Xudong Hao wrote:
> v3 changes from v2:
> - Refine code following by the qemu code style
> - As suggestion by Stefano, cheanup code, add some code comment
>
> v2 changes from v1:
> - Rebase to qemu upstream from qemu-xen
>
> Currently it is assumed PCI device BAR access < 4G memory. If there is such a
> device whose BAR size is larger than 4G, it must access > 4G memory address.
> This patch enable the 64bits big BAR support on qemu.
>
> Signed-off-by: Xudong Hao <xudong.hao@intel.com>
> Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> hw/xen_pt.c | 7 +++++--
> hw/xen_pt_config_init.c | 39 ++++++++++++++++++++++++++-------------
> 2 files changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/hw/xen_pt.c b/hw/xen_pt.c
> index 307119a..838bcea 100644
> --- a/hw/xen_pt.c
> +++ b/hw/xen_pt.c
> @@ -410,14 +410,17 @@ static int xen_pt_register_regions(XenPCIPassthroughState *s)
> if (r->type & XEN_HOST_PCI_REGION_TYPE_PREFETCH) {
> type |= PCI_BASE_ADDRESS_MEM_PREFETCH;
> }
> + if (r->type & XEN_HOST_PCI_REGION_TYPE_MEM_64) {
> + type |= PCI_BASE_ADDRESS_MEM_TYPE_64;
> + }
> }
>
> memory_region_init_io(&s->bar[i], &ops, &s->dev,
> "xen-pci-pt-bar", r->size);
> pci_register_bar(&s->dev, i, type, &s->bar[i]);
>
> - XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%08"PRIx64
> - " base_addr=0x%08"PRIx64" type: %#x)\n",
> + XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%lx"PRIx64
> + " base_addr=0x%lx"PRIx64" type: %#x)\n",
> i, r->size, r->base_addr, type);
> }
>
> diff --git a/hw/xen_pt_config_init.c b/hw/xen_pt_config_init.c
> index e524a40..0a5f82c 100644
> --- a/hw/xen_pt_config_init.c
> +++ b/hw/xen_pt_config_init.c
> @@ -342,6 +342,23 @@ static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
> #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
> #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
>
> +static bool is_64bit_bar(PCIIORegion *r)
> +{
> + return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
> +}
> +
> +static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
> +{
> + if (is_64bit_bar(r)) {
> + uint64_t size64;
> + size64 = (r + 1)->size;
> + size64 <<= 32;
> + size64 += r->size;
> + return size64;
> + }
> + return r->size;
> +}
> +
> static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
> XenPTRegInfo *reg)
> {
> @@ -366,7 +383,7 @@ static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
>
> /* check unused BAR */
> r = &d->io_regions[index];
> - if (r->size == 0) {
> + if (!xen_pt_get_bar_size(r)) {
> return XEN_PT_BAR_FLAG_UNUSED;
> }
>
> @@ -481,7 +498,12 @@ static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
> switch (s->bases[index].bar_flag) {
> case XEN_PT_BAR_FLAG_MEM:
> bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
> - bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
> + if (!r_size) {
> + /* low 32 bits mask for 64 bit bars */
> + bar_ro_mask = XEN_PT_BAR_ALLF;
> + } else {
> + bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
> + }
> break;
> case XEN_PT_BAR_FLAG_IO:
> bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
> @@ -489,7 +511,7 @@ static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
> break;
> case XEN_PT_BAR_FLAG_UPPER:
> bar_emu_mask = XEN_PT_BAR_ALLF;
> - bar_ro_mask = 0; /* all upper 32bit are R/W */
> + bar_ro_mask = r_size ? r_size - 1 : 0;
> break;
> default:
> break;
> @@ -501,22 +523,13 @@ static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
>
> /* check whether we need to update the virtual region address or not */
> switch (s->bases[index].bar_flag) {
> + case XEN_PT_BAR_FLAG_UPPER:
> case XEN_PT_BAR_FLAG_MEM:
> /* nothing to do */
> break;
> case XEN_PT_BAR_FLAG_IO:
> /* nothing to do */
> break;
> - case XEN_PT_BAR_FLAG_UPPER:
> - if (cfg_entry->data) {
> - if (cfg_entry->data != (XEN_PT_BAR_ALLF & ~bar_ro_mask)) {
> - XEN_PT_WARN(d, "Guest attempt to set high MMIO Base Address. "
> - "Ignore mapping. "
> - "(offset: 0x%02x, high address: 0x%08x)\n",
> - reg->offset, cfg_entry->data);
> - }
> - }
> - break;
> default:
> break;
> }
> --
> 1.5.5
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2012-09-27 3:01 [Qemu-devel] [PATCH v3] qemu/xen: Add 64 bits big bar support on qemu Xudong Hao
2012-09-27 10:06 ` Stefano Stabellini
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