From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOvN-0001F1-6U for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:59:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THOvK-0006tJ-NZ for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:59:25 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:58693) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOvK-0006tE-Gv for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:59:22 -0400 Received: by pbbrp2 with SMTP id rp2so4385803pbb.4 for ; Thu, 27 Sep 2012 17:59:21 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 27 Sep 2012 17:59:17 -0700 Message-Id: <1348793957-27999-1-git-send-email-rth@twiddle.net> In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 123/147] target-s390: Implement R[NOX]SBG List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexander Graf Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 4 ++++ target-s390x/translate.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 8bcfb2b..9582f0c 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -508,6 +508,10 @@ C(0xec55, RISBG, RIE_f, GIE, 0, r2, r1, 0, risbg, s64) C(0xec5d, RISBHG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) C(0xec51, RISBLG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) +/* ROTATE_THEN SELECTED BITS */ + C(0xec54, RNSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0) + C(0xec56, ROSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0) + C(0xec57, RXSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0) /* SEARCH STRING */ C(0xb25e, SRST, RRE, Z, r1_o, r2_o, 0, 0, srst, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 3fa0213..4489126 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2512,6 +2512,59 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_rosbg(DisasContext *s, DisasOps *o) +{ + int i3 = get_field(s->fields, i3); + int i4 = get_field(s->fields, i4); + int i5 = get_field(s->fields, i5); + uint64_t mask; + + /* If this is a test-only form, arrange to discard the result. */ + if (i3 & 0x80) { + o->out = tcg_temp_new_i64(); + o->g_out = false; + } + + i3 &= 63; + i4 &= 63; + i5 &= 63; + + /* MASK is the set of bits to be operated on from R2. + Take care for I3/I4 wraparound. */ + mask = ~0ull >> i3; + if (i3 <= i4) { + mask ^= ~0ull >> i4 >> 1; + } else { + mask |= ~(~0ull >> i4 >> 1); + } + + /* Rotate the input as necessary. */ + tcg_gen_rotli_i64(o->in2, o->in2, i5); + + /* Operate. */ + switch (s->fields->op2) { + case 0x55: /* AND */ + tcg_gen_ori_i64(o->in2, o->in2, ~mask); + tcg_gen_and_i64(o->out, o->out, o->in2); + break; + case 0x56: /* OR */ + tcg_gen_andi_i64(o->in2, o->in2, mask); + tcg_gen_or_i64(o->out, o->out, o->in2); + break; + case 0x57: /* XOR */ + tcg_gen_andi_i64(o->in2, o->in2, mask); + tcg_gen_xor_i64(o->out, o->out, o->in2); + break; + default: + abort(); + } + + /* Set the CC. */ + tcg_gen_andi_i64(cc_dst, o->out, mask); + set_cc_nz_u64(s, cc_dst); + return NO_EXIT; +} + static ExitStatus op_rev16(DisasContext *s, DisasOps *o) { tcg_gen_bswap16_i64(o->out, o->in2); -- 1.7.11.4