From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 01/14] i386: use OT_* consistently
Date: Sat, 6 Oct 2012 14:30:08 +0200 [thread overview]
Message-ID: <1349526621-13939-2-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1349526621-13939-1-git-send-email-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-i386/translate.c | 74 ++++++++++++++++++++++++-------------------------
1 file modificato, 37 inserzioni(+), 37 rimozioni(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 0a7e4e3..e2ef410 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -323,17 +323,17 @@ static inline void gen_op_mov_reg_T1(int ot, int reg)
static inline void gen_op_mov_reg_A0(int size, int reg)
{
switch(size) {
- case 0:
+ case OT_BYTE:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
break;
default: /* XXX this shouldn't be reached; abort? */
- case 1:
+ case OT_WORD:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
break;
#ifdef TARGET_X86_64
- case 2:
+ case OT_LONG:
tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
break;
#endif
@@ -398,11 +398,11 @@ static inline void gen_op_jmp_T0(void)
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
{
switch(size) {
- case 0:
+ case OT_BYTE:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
- case 1:
+ case OT_WORD:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
@@ -410,7 +410,7 @@ static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
- case 2:
+ case OT_LONG:
tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
break;
#endif
@@ -420,11 +420,11 @@ static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
static inline void gen_op_add_reg_T0(int size, int reg)
{
switch(size) {
- case 0:
+ case OT_BYTE:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
- case 1:
+ case OT_WORD:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
@@ -432,7 +432,7 @@ static inline void gen_op_add_reg_T0(int size, int reg)
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
- case 2:
+ case OT_LONG:
tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
break;
#endif
@@ -506,14 +506,14 @@ static inline void gen_op_lds_T0_A0(int idx)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
- case 0:
+ case OT_BYTE:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
break;
- case 1:
+ case OT_WORD:
tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
break;
default:
- case 2:
+ case OT_LONG:
tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
break;
}
@@ -523,17 +523,17 @@ static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
- case 0:
+ case OT_BYTE:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
break;
- case 1:
+ case OT_WORD:
tcg_gen_qemu_ld16u(t0, a0, mem_index);
break;
- case 2:
+ case OT_LONG:
tcg_gen_qemu_ld32u(t0, a0, mem_index);
break;
default:
- case 3:
+ case OT_QUAD:
/* Should never happen on 32-bit targets. */
#ifdef TARGET_X86_64
tcg_gen_qemu_ld64(t0, a0, mem_index);
@@ -562,17 +562,17 @@ static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
- case 0:
+ case OT_BYTE:
tcg_gen_qemu_st8(t0, a0, mem_index);
break;
- case 1:
+ case OT_WORD:
tcg_gen_qemu_st16(t0, a0, mem_index);
break;
- case 2:
+ case OT_LONG:
tcg_gen_qemu_st32(t0, a0, mem_index);
break;
default:
- case 3:
+ case OT_QUAD:
/* Should never happen on 32-bit targets. */
#ifdef TARGET_X86_64
tcg_gen_qemu_st64(t0, a0, mem_index);
@@ -710,9 +710,9 @@ static inline void gen_op_jz_ecx(int size, int label1)
static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
- case 0: gen_helper_inb(v, n); break;
- case 1: gen_helper_inw(v, n); break;
- case 2: gen_helper_inl(v, n); break;
+ case OT_BYTE: gen_helper_inb(v, n); break;
+ case OT_WORD: gen_helper_inw(v, n); break;
+ case OT_LONG: gen_helper_inl(v, n); break;
}
}
@@ -720,9 +720,9 @@ static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
- case 0: gen_helper_outb(v, n); break;
- case 1: gen_helper_outw(v, n); break;
- case 2: gen_helper_outl(v, n); break;
+ case OT_BYTE: gen_helper_outb(v, n); break;
+ case OT_WORD: gen_helper_outw(v, n); break;
+ case OT_LONG: gen_helper_outl(v, n); break;
}
}
@@ -741,13 +741,13 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
state_saved = 1;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
switch (ot) {
- case 0:
+ case OT_BYTE:
gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
break;
- case 1:
+ case OT_WORD:
gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
break;
- case 2:
+ case OT_LONG:
gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
break;
}
@@ -1781,34 +1781,34 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
if (is_right) {
switch (ot) {
- case 0:
+ case OT_BYTE:
gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case 1:
+ case OT_WORD:
gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case 2:
+ case OT_LONG:
gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#ifdef TARGET_X86_64
- case 3:
+ case OT_QUAD:
gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
}
} else {
switch (ot) {
- case 0:
+ case OT_BYTE:
gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case 1:
+ case OT_WORD:
gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case 2:
+ case OT_LONG:
gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#ifdef TARGET_X86_64
- case 3:
+ case OT_QUAD:
gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
--
1.7.12.1
next prev parent reply other threads:[~2012-10-06 12:30 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-06 12:30 [Qemu-devel] [CFT PATCH 00/14] Improve handling of x86 condition codes (tcg) Paolo Bonzini
2012-10-06 12:30 ` Paolo Bonzini [this message]
2012-10-07 18:50 ` [Qemu-devel] [PATCH 01/14] i386: use OT_* consistently Blue Swirl
2012-10-09 18:58 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 02/14] i386: introduce gen_ext_tl Paolo Bonzini
2012-10-07 18:53 ` Blue Swirl
2012-10-09 18:58 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 03/14] i386: factor setting of s->cc_op handling for string functions Paolo Bonzini
2012-10-09 18:59 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 04/14] i386: drop cc_op argument of gen_jcc1 Paolo Bonzini
2012-10-09 18:59 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 05/14] i386: move eflags computation closer to gen_op_set_cc_op Paolo Bonzini
2012-10-09 19:02 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 06/14] i386: factor gen_op_set_cc_op/tcg_gen_discard_tl around computing flags Paolo Bonzini
2012-10-09 19:03 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 07/14] i386: add helper functions to get other flags Paolo Bonzini
2012-10-07 19:04 ` Blue Swirl
2012-10-09 19:04 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 08/14] i386: do not compute eflags multiple times consecutively Paolo Bonzini
2012-10-07 19:09 ` Blue Swirl
2012-10-09 19:14 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 09/14] i386: do not call helper to compute ZF/SF Paolo Bonzini
2012-10-07 19:16 ` Blue Swirl
2012-10-09 19:15 ` Richard Henderson
2012-10-09 19:16 ` Richard Henderson
2012-10-10 6:42 ` Paolo Bonzini
2012-10-06 12:30 ` [Qemu-devel] [PATCH 10/14] i386: use inverted setcond when computing NS or NZ Paolo Bonzini
2012-10-07 19:19 ` Blue Swirl
2012-10-09 19:17 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 11/14] i386: convert gen_compute_eflags_c to TCG Paolo Bonzini
2012-10-07 19:35 ` Blue Swirl
2012-10-09 20:07 ` Richard Henderson
2012-10-10 6:47 ` Paolo Bonzini
2012-10-06 12:30 ` [Qemu-devel] [PATCH 12/14] i386: change gen_setcc_slow_T0 to gen_setcc_slow Paolo Bonzini
2012-10-07 19:36 ` Blue Swirl
2012-10-09 20:07 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 13/14] i386: optimize setbe Paolo Bonzini
2012-10-07 19:43 ` Blue Swirl
2012-10-09 20:13 ` Richard Henderson
2012-10-06 12:30 ` [Qemu-devel] [PATCH 14/14] i386: optimize setcc instructions Paolo Bonzini
2012-10-07 19:58 ` Blue Swirl
2012-10-09 20:22 ` Richard Henderson
2012-10-10 6:51 ` Paolo Bonzini
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