From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49692) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TKTWg-0004Hc-ME for qemu-devel@nongnu.org; Sat, 06 Oct 2012 08:30:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TKTWe-0000Ck-0V for qemu-devel@nongnu.org; Sat, 06 Oct 2012 08:30:38 -0400 Received: from mail-we0-f173.google.com ([74.125.82.173]:53432) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TKTWd-00005r-R0 for qemu-devel@nongnu.org; Sat, 06 Oct 2012 08:30:35 -0400 Received: by mail-we0-f173.google.com with SMTP id t11so1531985wey.4 for ; Sat, 06 Oct 2012 05:30:35 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Sat, 6 Oct 2012 14:30:14 +0200 Message-Id: <1349526621-13939-8-git-send-email-pbonzini@redhat.com> In-Reply-To: <1349526621-13939-1-git-send-email-pbonzini@redhat.com> References: <1349526621-13939-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 07/14] i386: add helper functions to get other flags List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Introduce new functions to extract PF, SF, OF, ZF in addition to CF. These provide single entry points for optimizing accesses to a single flag. Signed-off-by: Paolo Bonzini --- target-i386/translate.c | 48 ++++++++++++++++++++++++++++++++++++------------ 1 file modificato, 36 inserzioni(+), 12 rimozioni(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index df81b78..8f22119 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -847,21 +847,49 @@ static void gen_compute_eflags(DisasContext *s, TCGv reg) tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); } +/* compute eflags.P to reg */ +static void gen_compute_eflags_p(DisasContext *s, TCGv reg) +{ + gen_compute_eflags(s, reg); + tcg_gen_shri_tl(reg, reg, 2); + tcg_gen_andi_tl(reg, reg, 1); +} + +/* compute eflags.S to reg */ +static void gen_compute_eflags_s(DisasContext *s, TCGv reg) +{ + gen_compute_eflags(s, reg); + tcg_gen_shri_tl(reg, reg, 7); + tcg_gen_andi_tl(reg, reg, 1); +} + +/* compute eflags.O to reg */ +static void gen_compute_eflags_o(DisasContext *s, TCGv reg) +{ + gen_compute_eflags(s, reg); + tcg_gen_shri_tl(reg, reg, 11); + tcg_gen_andi_tl(reg, reg, 1); +} + +/* compute eflags.Z to reg */ +static void gen_compute_eflags_z(DisasContext *s, TCGv reg) +{ + gen_compute_eflags(s, reg); + tcg_gen_shri_tl(reg, reg, 6); + tcg_gen_andi_tl(reg, reg, 1); +} + static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) { switch(jcc_op) { case JCC_O: - gen_compute_eflags(s, cpu_T[0]); - tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + gen_compute_eflags_o(s, cpu_T[0]); break; case JCC_B: gen_compute_eflags_c(s, cpu_T[0]); break; case JCC_Z: - gen_compute_eflags(s, cpu_T[0]); - tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + gen_compute_eflags_z(s, cpu_T[0]); break; case JCC_BE: gen_compute_eflags(s, cpu_tmp0); @@ -870,14 +898,10 @@ static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); break; case JCC_S: - gen_compute_eflags(s, cpu_T[0]); - tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + gen_compute_eflags_s(s, cpu_T[0]); break; case JCC_P: - gen_compute_eflags(s, cpu_T[0]); - tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + gen_compute_eflags_p(s, cpu_T[0]); break; case JCC_L: gen_compute_eflags(s, cpu_tmp0); -- 1.7.12.1