From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP5-0007Mt-F1 for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgP2-0004P9-OW for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:47 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45239) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP2-0004Ok-Gd for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:44 -0400 From: Aurelien Jarno Date: Tue, 9 Oct 2012 22:27:33 +0200 Message-Id: <1349814458-21739-10-git-send-email-aurelien@aurel32.net> In-Reply-To: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> References: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 09/14] target-mips: don't use local temps for store conditional List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno Store conditional operations only need local temps in user mode. Fix the code to use temp local only in user mode, this spares two memory stores in system mode. At the same time remove a wrong a wrong copied & pasted comment, store operations don't have a register destination. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 8a7462b..b6eb46a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1375,13 +1375,14 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, const char *opn = "st_cond"; TCGv t0, t1; +#ifdef CONFIG_USER_ONLY t0 = tcg_temp_local_new(); - - gen_base_offset_addr(ctx, t0, base, offset); - /* Don't do NOP if destination is zero: we must perform the actual - memory access. */ - t1 = tcg_temp_local_new(); +#else + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); +#endif + gen_base_offset_addr(ctx, t0, base, offset); gen_load_gpr(t1, rt); switch (opc) { #if defined(TARGET_MIPS64) -- 1.7.10.4