From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLhus-0004fO-Iy for qemu-devel@nongnu.org; Tue, 09 Oct 2012 18:04:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLhur-0001jB-Gv for qemu-devel@nongnu.org; Tue, 09 Oct 2012 18:04:42 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:34860) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLhur-0001fh-Af for qemu-devel@nongnu.org; Tue, 09 Oct 2012 18:04:41 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so5751708pbb.4 for ; Tue, 09 Oct 2012 15:04:41 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 9 Oct 2012 15:04:16 -0700 Message-Id: <1349820267-26320-10-git-send-email-rth@twiddle.net> In-Reply-To: <1349820267-26320-1-git-send-email-rth@twiddle.net> References: <1349820267-26320-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl Signed-off-by: Richard Henderson --- target-sparc/translate.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index e3e4256..5296a37 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -125,6 +125,22 @@ static int sign_extend(int x, int len) #define IS_IMM (insn & (1<<13)) +static inline TCGv_i32 get_temp_i32(DisasContext *dc) +{ + TCGv_i32 t; + assert(dc->n_t32 < ARRAY_SIZE(dc->t32)); + dc->t32[dc->n_t32++] = t = tcg_temp_new_i32(); + return t; +} + +static inline TCGv get_temp_tl(DisasContext *dc) +{ + TCGv t; + assert(dc->n_ttl < ARRAY_SIZE(dc->ttl)); + dc->ttl[dc->n_ttl++] = t = tcg_temp_new(); + return t; +} + static inline void gen_update_fprs_dirty(int rd) { #if defined(TARGET_SPARC64) @@ -145,16 +161,13 @@ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) if (src & 1) { return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2])); } else { - TCGv_i32 ret = tcg_temp_new_i32(); + TCGv_i32 ret = get_temp_i32(dc); TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32); tcg_gen_trunc_i64_i32(ret, t); tcg_temp_free_i64(t); - dc->t32[dc->n_t32++] = ret; - assert(dc->n_t32 <= ARRAY_SIZE(dc->t32)); - return ret; } #endif @@ -265,14 +278,6 @@ static inline void gen_address_mask(DisasContext *dc, TCGv addr) #endif } -static inline TCGv get_temp_tl(DisasContext *dc) -{ - TCGv t; - assert(dc->n_ttl < ARRAY_SIZE(dc->ttl)); - dc->ttl[dc->n_ttl++] = t = tcg_temp_new(); - return t; -} - static inline TCGv gen_load_gpr(DisasContext *dc, int reg) { if (reg == 0 || reg >= 8) { -- 1.7.11.4