* [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps
@ 2012-10-09 22:04 Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr Richard Henderson
` (20 more replies)
0 siblings, 21 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
The primary goal of this patch set is to have all references to windowed
registers to go through new routines that have access to DisasContext.
This is a prerequisite to any change in how windowed registers might be
managed.
Since such a goal must of course touch get_src[12], and therefore touch
the use of the cpu_src[12] temporaries, a secondary goal of the patch set
became to clean up all of the temporary management within the translator.
And in particular eliminate the 6 "global" temps that we currently allocate
inside gen_intermediate_code_internal.
In some cases we convert their uses to simple temps allocated and freed
nearby their uses. In some cases we push the cpu_foo temp down into the
disassembly of a given opcode, making it local to the code that ought to
be able to access it. And finally we provide for temps to be allocated
dynamically, and then automatically freed at the end of the insn.
The result ought to be microscopically faster than before, if only
because TCG is iterating over fewer temporaries.
r~
Richard Henderson (20):
target-sparc: Add gen_load/store/dest_gpr
target-sparc: Conversion to gen_*_gpr, part 1
target-sparc: Use gen_load_gpr in get_src[12]
target-sparc: Convert asi helpers to gen_*_gpr
target-sparc: Convert swap to gen_load/store_gpr
target-sparc: Finish conversion to gen_load_gpr
target-sparc: Cleanup cpu_src[12] allocation
target-sparc: Make the cpu_addr variable local to load/store handling
target-sparc: Split out get_temp_i32
target-sparc: Use get_temp_i32 in gen_dest_fpr_F
target-sparc: Avoid cpu_tmp32 in Read Priv Register
target-sparc: Avoid cpu_tmp32 in Write Priv Register
target-sparc: Tidy ldfsr, stfsr
target-sparc: Remove usage of cpu_tmp64 from most helper functions
target-sparc: Don't use a temporary for gen_dest_fpr_D
target-sparc: Remove cpu_tmp64 use from softint insns
target-sparc: Remove last uses of cpu_tmp64
target-sparc: Only use cpu_dst for eventual writes to a gpr
target-sparc: Make cpu_dst local to OP=2 insns
target-sparc: Remove cpu_tmp0 as a global
target-sparc/translate.c | 1233 +++++++++++++++++++++++-----------------------
1 file changed, 609 insertions(+), 624 deletions(-)
--
1.7.11.4
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 02/20] target-sparc: Conversion to gen_*_gpr, part 1 Richard Henderson
` (19 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Infrastructure to be used to clean up handling of temporaries.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 6cef96b..eec0db0 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -83,7 +83,9 @@ typedef struct DisasContext {
struct TranslationBlock *tb;
sparc_def_t *def;
TCGv_i32 t32[3];
+ TCGv ttl[5];
int n_t32;
+ int n_ttl;
} DisasContext;
typedef struct {
@@ -263,6 +265,49 @@ static inline void gen_address_mask(DisasContext *dc, TCGv addr)
#endif
}
+static inline TCGv get_temp_tl(DisasContext *dc)
+{
+ TCGv t;
+ assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
+ dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
+ return t;
+}
+
+static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
+{
+ if (reg == 0 || reg >= 8) {
+ TCGv t = get_temp_tl(dc);
+ if (reg == 0) {
+ tcg_gen_movi_tl(t, 0);
+ } else {
+ tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
+ }
+ return t;
+ } else {
+ return cpu_gregs[reg];
+ }
+}
+
+static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
+{
+ if (reg > 0) {
+ if (reg < 8) {
+ tcg_gen_mov_tl(cpu_gregs[reg], v);
+ } else {
+ tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
+ }
+ }
+}
+
+static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
+{
+ if (reg == 0 || reg >= 8) {
+ return get_temp_tl(dc);
+ } else {
+ return cpu_gregs[reg];
+ }
+}
+
static inline void gen_movl_reg_TN(int reg, TCGv tn)
{
if (reg == 0)
@@ -5229,6 +5274,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
dc->n_t32 = 0;
}
+ if (dc->n_ttl != 0) {
+ int i;
+ for (i = dc->n_ttl - 1; i >= 0; --i) {
+ tcg_temp_free(dc->ttl[i]);
+ }
+ dc->n_ttl = 0;
+ }
}
static inline void gen_intermediate_code_internal(TranslationBlock * tb,
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 02/20] target-sparc: Conversion to gen_*_gpr, part 1
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 03/20] target-sparc: Use gen_load_gpr in get_src[12] Richard Henderson
` (18 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Only handle the easy cases directly within disas_sparc_insn.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 420 ++++++++++++++++++++---------------------------
1 file changed, 177 insertions(+), 243 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index eec0db0..0ec3d48 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2602,13 +2602,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto jmp_insn;
}
case 0x4: /* SETHI */
- if (rd) { // nop
+ /* Special-case %g0 because that's the canonical nop. */
+ if (rd) {
uint32_t value = GET_FIELD(insn, 10, 31);
- TCGv r_const;
-
- r_const = tcg_const_tl(value << 10);
- gen_movl_TN_reg(rd, r_const);
- tcg_temp_free(r_const);
+ TCGv t = gen_dest_gpr(dc, rd);
+ tcg_gen_movi_tl(t, value << 10);
+ gen_store_gpr(dc, rd, t);
}
break;
case 0x0: /* UNIMPL */
@@ -2621,11 +2620,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 1: /*CALL*/
{
target_long target = GET_FIELDs(insn, 2, 31) << 2;
- TCGv r_const;
+ TCGv o7 = gen_dest_gpr(dc, 15);
- r_const = tcg_const_tl(dc->pc);
- gen_movl_TN_reg(15, r_const);
- tcg_temp_free(r_const);
+ tcg_gen_movi_tl(o7, dc->pc);
+ gen_store_gpr(dc, 15, o7);
target += dc->pc;
gen_mov_pc_npc(dc);
#ifdef TARGET_SPARC64
@@ -2689,22 +2687,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
/* Signal that the trap value is fully constant. */
mask = 0;
} else {
- TCGv t1 = tcg_temp_new();
- gen_movl_reg_TN(rs1, t1);
+ TCGv t1 = gen_load_gpr(dc, rs1);
tcg_gen_trunc_tl_i32(trap, t1);
- tcg_temp_free(t1);
tcg_gen_addi_i32(trap, trap, rs2);
}
} else {
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
+ TCGv t1, t2;
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_TN(rs1, t1);
- gen_movl_reg_TN(rs2, t2);
+ t1 = gen_load_gpr(dc, rs1);
+ t2 = gen_load_gpr(dc, rs2);
tcg_gen_add_tl(t1, t1, t2);
tcg_gen_trunc_tl_i32(trap, t1);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
}
if (mask != 0) {
tcg_gen_andi_i32(trap, trap, mask);
@@ -2738,27 +2731,24 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
microSPARC II */
/* Read Asr17 */
if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
- TCGv r_const;
-
+ TCGv t = gen_dest_gpr(dc, rd);
/* Read Asr17 for a Leon3 monoprocessor */
- r_const = tcg_const_tl((1 << 8)
- | (dc->def->nwindows - 1));
- gen_movl_TN_reg(rd, r_const);
- tcg_temp_free(r_const);
+ tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
+ gen_store_gpr(dc, rd, t);
break;
}
#endif
- gen_movl_TN_reg(rd, cpu_y);
+ gen_store_gpr(dc, rd, cpu_y);
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */
update_psr(dc);
gen_helper_rdccr(cpu_dst, cpu_env);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x3: /* V9 rdasi */
tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x4: /* V9 rdtick */
{
@@ -2769,25 +2759,23 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
offsetof(CPUSPARCState, tick));
gen_helper_tick_get_count(cpu_dst, r_tickptr);
tcg_temp_free_ptr(r_tickptr);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
}
break;
case 0x5: /* V9 rdpc */
{
- TCGv r_const;
-
+ TCGv t = gen_dest_gpr(dc, rd);
if (unlikely(AM_CHECK(dc))) {
- r_const = tcg_const_tl(dc->pc & 0xffffffffULL);
+ tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
} else {
- r_const = tcg_const_tl(dc->pc);
+ tcg_gen_movi_tl(t, dc->pc);
}
- gen_movl_TN_reg(rd, r_const);
- tcg_temp_free(r_const);
+ gen_store_gpr(dc, rd, t);
}
break;
case 0x6: /* V9 rdfprs */
tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0xf: /* V9 membar */
break; /* no effect */
@@ -2795,14 +2783,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
- gen_movl_TN_reg(rd, cpu_gsr);
+ gen_store_gpr(dc, rd, cpu_gsr);
break;
case 0x16: /* Softint */
tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x17: /* Tick compare */
- gen_movl_TN_reg(rd, cpu_tick_cmpr);
+ gen_store_gpr(dc, rd, cpu_tick_cmpr);
break;
case 0x18: /* System tick */
{
@@ -2813,11 +2801,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
offsetof(CPUSPARCState, stick));
gen_helper_tick_get_count(cpu_dst, r_tickptr);
tcg_temp_free_ptr(r_tickptr);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
}
break;
case 0x19: /* System tick compare */
- gen_movl_TN_reg(rd, cpu_stick_cmpr);
+ gen_store_gpr(dc, rd, cpu_stick_cmpr);
break;
case 0x10: /* Performance Control */
case 0x11: /* Performance Instrumentation Counter */
@@ -2864,7 +2852,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
}
#endif
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
if (!supervisor(dc))
@@ -2925,7 +2913,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
- gen_movl_TN_reg(rd, cpu_tmp0);
tcg_temp_free_ptr(r_tickptr);
}
break;
@@ -2997,7 +2984,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#else
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
#endif
- gen_movl_TN_reg(rd, cpu_tmp0);
+ gen_store_gpr(dc, rd, cpu_tmp0);
break;
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
#ifdef TARGET_SPARC64
@@ -3006,7 +2993,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#else
if (!supervisor(dc))
goto priv_insn;
- gen_movl_TN_reg(rd, cpu_tbr);
+ gen_store_gpr(dc, rd, cpu_tbr);
#endif
break;
#endif
@@ -3338,38 +3325,40 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
}
} else if (xop == 0x2) {
- // clr/mov shortcut
-
+ TCGv dst = gen_dest_gpr(dc, rd);
rs1 = GET_FIELD(insn, 13, 17);
if (rs1 == 0) {
- // or %g0, x, y -> mov T0, x; mov y, T0
+ /* clr/mov shortcut : or %g0, x, y -> mov x, y */
if (IS_IMM) { /* immediate */
- TCGv r_const;
-
simm = GET_FIELDs(insn, 19, 31);
- r_const = tcg_const_tl(simm);
- gen_movl_TN_reg(rd, r_const);
- tcg_temp_free(r_const);
+ tcg_gen_movi_tl(dst, simm);
+ gen_store_gpr(dc, rd, dst);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_TN(rs2, cpu_dst);
- gen_movl_TN_reg(rd, cpu_dst);
+ if (rs2 == 0) {
+ tcg_gen_movi_tl(dst, 0);
+ gen_store_gpr(dc, rd, dst);
+ } else {
+ cpu_src2 = gen_load_gpr(dc, rs2);
+ gen_store_gpr(dc, rd, cpu_src2);
+ }
}
} else {
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
- gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_ori_tl(dst, cpu_src1, simm);
+ gen_store_gpr(dc, rd, dst);
} else { /* register */
- // or x, %g0, y -> mov T1, x; mov y, T1
rs2 = GET_FIELD(insn, 27, 31);
- if (rs2 != 0) {
- gen_movl_reg_TN(rs2, cpu_src2);
- tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
- } else
- gen_movl_TN_reg(rd, cpu_src1);
+ if (rs2 == 0) {
+ /* mov shortcut: or x, %g0, y -> mov x, y */
+ gen_store_gpr(dc, rd, cpu_src1);
+ } else {
+ cpu_src2 = gen_load_gpr(dc, rs2);
+ tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
+ gen_store_gpr(dc, rd, dst);
+ }
}
}
#ifdef TARGET_SPARC64
@@ -3384,7 +3373,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
} else {
@@ -3392,7 +3381,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
}
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
} else if (xop == 0x26) { /* srl, V9 srlx */
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
@@ -3405,7 +3394,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
@@ -3415,7 +3404,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
}
}
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
} else if (xop == 0x27) { /* sra, V9 srax */
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
@@ -3423,24 +3412,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (insn & (1 << 12)) {
tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
} else {
- tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
- tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
+ tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
} else {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
- tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
- tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
+ tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
}
}
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
#endif
} else if (xop < 0x36) {
if (xop < 0x20) {
@@ -3448,32 +3435,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cpu_src2 = get_src2(insn, cpu_src2);
switch (xop & ~0x10) {
case 0x0: /* add */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- if (xop & 0x10) {
- gen_op_addi_cc(cpu_dst, cpu_src1, simm);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
- dc->cc_op = CC_OP_ADD;
- } else {
- tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
- }
+ if (xop & 0x10) {
+ gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
+ dc->cc_op = CC_OP_ADD;
} else {
- if (xop & 0x10) {
- gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
- dc->cc_op = CC_OP_ADD;
- } else {
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
}
break;
case 0x1: /* and */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
- } else {
- tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
@@ -3481,12 +3452,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
break;
case 0x2: /* or */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
- } else {
- tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
@@ -3494,12 +3460,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
break;
case 0x3: /* xor */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
- } else {
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
@@ -3507,30 +3468,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
break;
case 0x4: /* sub */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- if (xop & 0x10) {
- gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
- } else {
- tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
- }
+ if (xop & 0x10) {
+ gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
+ dc->cc_op = CC_OP_SUB;
} else {
- if (xop & 0x10) {
- gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
- dc->cc_op = CC_OP_SUB;
- } else {
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
}
break;
case 0x5: /* andn */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
- } else {
- tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
@@ -3538,12 +3485,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
break;
case 0x6: /* orn */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
- } else {
- tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
@@ -3551,13 +3493,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
break;
case 0x7: /* xorn */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
- } else {
- tcg_gen_not_tl(cpu_tmp0, cpu_src2);
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
+ tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
@@ -3570,12 +3506,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
#ifdef TARGET_SPARC64
case 0x9: /* V9 mulx */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_muli_i64(cpu_dst, cpu_src1, simm);
- } else {
- tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
- }
+ tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
break;
#endif
case 0xa: /* umul */
@@ -3630,39 +3561,39 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
default:
goto illegal_insn;
}
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
} else {
cpu_src1 = get_src1(insn, cpu_src1);
cpu_src2 = get_src2(insn, cpu_src2);
switch (xop) {
case 0x20: /* taddcc */
gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
dc->cc_op = CC_OP_TADD;
break;
case 0x21: /* tsubcc */
gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
dc->cc_op = CC_OP_TSUB;
break;
case 0x22: /* taddcctv */
gen_helper_taddcctv(cpu_dst, cpu_env,
cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
dc->cc_op = CC_OP_TADDTV;
break;
case 0x23: /* tsubcctv */
gen_helper_tsubcctv(cpu_dst, cpu_env,
cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
dc->cc_op = CC_OP_TSUBTV;
break;
case 0x24: /* mulscc */
update_psr(dc);
gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
dc->cc_op = CC_OP_ADD;
break;
@@ -3675,7 +3606,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x26: /* srl */
if (IS_IMM) { /* immediate */
@@ -3685,7 +3616,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x27: /* sra */
if (IS_IMM) { /* immediate */
@@ -3695,7 +3626,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
#endif
case 0x30:
@@ -4059,6 +3990,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
int cc = GET_FIELD_SP(insn, 11, 12);
int cond = GET_FIELD_SP(insn, 14, 17);
DisasCompare cmp;
+ TCGv dst;
if (insn & (1 << 18)) {
if (cc == 0) {
@@ -4080,28 +4012,27 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_movi_tl(cpu_src2, simm);
}
- gen_movl_reg_TN(rd, cpu_dst);
- tcg_gen_movcond_tl(cmp.cond, cpu_dst,
+ dst = gen_load_gpr(dc, rd);
+ tcg_gen_movcond_tl(cmp.cond, dst,
cmp.c1, cmp.c2,
- cpu_src2, cpu_dst);
+ cpu_src2, dst);
free_compare(&cmp);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, dst);
break;
}
case 0x2d: /* V9 sdivx */
gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x2e: /* V9 popc */
- {
- cpu_src2 = get_src2(insn, cpu_src2);
- gen_helper_popc(cpu_dst, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
- }
+ gen_helper_popc(cpu_dst, cpu_src2);
+ gen_store_gpr(dc, rd, cpu_dst);
+ break;
case 0x2f: /* V9 movr */
{
int cond = GET_FIELD_SP(insn, 10, 12);
DisasCompare cmp;
+ TCGv dst;
gen_compare_reg(&cmp, cond, cpu_src1);
@@ -4113,12 +4044,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_movi_tl(cpu_src2, simm);
}
- gen_movl_reg_TN(rd, cpu_dst);
- tcg_gen_movcond_tl(cmp.cond, cpu_dst,
+ dst = gen_load_gpr(dc, rd);
+ tcg_gen_movcond_tl(cmp.cond, dst,
cmp.c1, cmp.c2,
- cpu_src2, cpu_dst);
+ cpu_src2, dst);
free_compare(&cmp);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, dst);
break;
}
#endif
@@ -4138,188 +4069,188 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
switch (opf) {
case 0x000: /* VIS I edge8cc */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x001: /* VIS II edge8n */
CHECK_FPU_FEATURE(dc, VIS2);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x002: /* VIS I edge8lcc */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x003: /* VIS II edge8ln */
CHECK_FPU_FEATURE(dc, VIS2);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x004: /* VIS I edge16cc */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x005: /* VIS II edge16n */
CHECK_FPU_FEATURE(dc, VIS2);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x006: /* VIS I edge16lcc */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x007: /* VIS II edge16ln */
CHECK_FPU_FEATURE(dc, VIS2);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x008: /* VIS I edge32cc */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x009: /* VIS II edge32n */
CHECK_FPU_FEATURE(dc, VIS2);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x00a: /* VIS I edge32lcc */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x00b: /* VIS II edge32ln */
CHECK_FPU_FEATURE(dc, VIS2);
- gen_movl_reg_TN(rs1, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x010: /* VIS I array8 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x012: /* VIS I array16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x014: /* VIS I array32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x018: /* VIS I alignaddr */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x01a: /* VIS I alignaddrl */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x019: /* VIS II bmask */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = get_src1(insn, cpu_src1);
- cpu_src2 = get_src1(insn, cpu_src2);
+ cpu_src2 = get_src2(insn, cpu_src2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x020: /* VIS I fcmple16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x022: /* VIS I fcmpne16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x024: /* VIS I fcmple32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x026: /* VIS I fcmpne32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x028: /* VIS I fcmpgt16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x02a: /* VIS I fcmpeq16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x02c: /* VIS I fcmpgt32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x02e: /* VIS I fcmpeq32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x031: /* VIS I fmul8x16 */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -4587,10 +4518,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2) {
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
- } else
+ } else {
tcg_gen_mov_tl(cpu_dst, cpu_src1);
+ }
}
gen_helper_restore(cpu_env);
gen_mov_pc_npc(dc);
@@ -4609,20 +4541,21 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2) {
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
- } else
+ } else {
tcg_gen_mov_tl(cpu_dst, cpu_src1);
+ }
}
switch (xop) {
case 0x38: /* jmpl */
{
- TCGv r_pc;
+ TCGv t;
TCGv_i32 r_const;
- r_pc = tcg_const_tl(dc->pc);
- gen_movl_TN_reg(rd, r_pc);
- tcg_temp_free(r_pc);
+ t = gen_dest_gpr(dc, rd);
+ tcg_gen_movi_tl(t, dc->pc);
+ gen_store_gpr(dc, rd, t);
gen_mov_pc_npc(dc);
r_const = tcg_const_i32(3);
gen_helper_check_align(cpu_env, cpu_dst, r_const);
@@ -4657,12 +4590,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x3c: /* save */
save_state(dc);
gen_helper_save(cpu_env);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x3d: /* restore */
save_state(dc);
gen_helper_restore(cpu_env);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_dst);
break;
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
case 0x3e: /* V9 done/retry */
@@ -4702,7 +4635,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cpu_src1 = get_src1(insn, cpu_src1);
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_mov_tl(cpu_addr, cpu_src1);
} else if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
@@ -4710,10 +4643,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 != 0) {
- gen_movl_reg_TN(rs2, cpu_src2);
+ cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
- } else
+ } else {
tcg_gen_mov_tl(cpu_addr, cpu_src1);
+ }
}
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
(xop > 0x17 && xop <= 0x1d ) ||
@@ -4746,7 +4680,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
- gen_movl_TN_reg(rd + 1, cpu_tmp0);
+ gen_store_gpr(dc, rd + 1, cpu_tmp0);
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
@@ -4924,7 +4858,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
default:
goto illegal_insn;
}
- gen_movl_TN_reg(rd, cpu_val);
+ gen_store_gpr(dc, rd, cpu_val);
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
skip_move: ;
#endif
@@ -5169,11 +5103,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x3c: /* V9 casa */
gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
- gen_movl_TN_reg(rd, cpu_val);
+ gen_store_gpr(dc, rd, cpu_val);
break;
case 0x3e: /* V9 casxa */
gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
- gen_movl_TN_reg(rd, cpu_val);
+ gen_store_gpr(dc, rd, cpu_val);
break;
#else
case 0x34: /* stc */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 03/20] target-sparc: Use gen_load_gpr in get_src[12]
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 02/20] target-sparc: Conversion to gen_*_gpr, part 1 Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 04/20] target-sparc: Convert asi helpers to gen_*_gpr Richard Henderson
` (17 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
This means we can avoid the incoming temporary, though the cleanup
of the existing temporaries is not performed in this patch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 75 +++++++++++++++++++-----------------------------
1 file changed, 29 insertions(+), 46 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0ec3d48..760cfd6 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2248,40 +2248,23 @@ static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
}
#endif
-static inline TCGv get_src1(unsigned int insn, TCGv def)
+static TCGv get_src1(DisasContext *dc, unsigned int insn)
{
- TCGv r_rs1 = def;
- unsigned int rs1;
-
- rs1 = GET_FIELD(insn, 13, 17);
- if (rs1 == 0) {
- tcg_gen_movi_tl(def, 0);
- } else if (rs1 < 8) {
- r_rs1 = cpu_gregs[rs1];
- } else {
- tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
- }
- return r_rs1;
+ unsigned int rs1 = GET_FIELD(insn, 13, 17);
+ return gen_load_gpr(dc, rs1);
}
-static inline TCGv get_src2(unsigned int insn, TCGv def)
+static TCGv get_src2(DisasContext *dc, unsigned int insn)
{
- TCGv r_rs2 = def;
-
if (IS_IMM) { /* immediate */
target_long simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_movi_tl(def, simm);
- } else { /* register */
+ TCGv t = get_temp_tl(dc);
+ tcg_gen_movi_tl(t, simm);
+ return t;
+ } else { /* register */
unsigned int rs2 = GET_FIELD(insn, 27, 31);
- if (rs2 == 0) {
- tcg_gen_movi_tl(def, 0);
- } else if (rs2 < 8) {
- r_rs2 = cpu_gregs[rs2];
- } else {
- tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
- }
+ return gen_load_gpr(dc, rs2);
}
- return r_rs2;
}
#ifdef TARGET_SPARC64
@@ -2560,7 +2543,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
(GET_FIELD_SP(insn, 20, 21) << 14);
target = sign_extend(target, 16);
target <<= 2;
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
do_branch_reg(dc, target, insn, cpu_src1);
goto jmp_insn;
}
@@ -3187,7 +3170,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
do { \
DisasCompare cmp; \
cond = GET_FIELD_SP(insn, 14, 17); \
- cpu_src1 = get_src1(insn, cpu_src1); \
+ cpu_src1 = get_src1(dc, insn); \
gen_compare_reg(&cmp, cond, cpu_src1); \
gen_fmov##sz(dc, &cmp, rd, rs2); \
free_compare(&cmp); \
@@ -3344,7 +3327,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
}
} else {
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(dst, cpu_src1, simm);
@@ -3363,7 +3346,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
#ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx */
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
@@ -3383,7 +3366,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
gen_store_gpr(dc, rd, cpu_dst);
} else if (xop == 0x26) { /* srl, V9 srlx */
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
@@ -3406,7 +3389,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
gen_store_gpr(dc, rd, cpu_dst);
} else if (xop == 0x27) { /* sra, V9 srax */
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
@@ -3431,8 +3414,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#endif
} else if (xop < 0x36) {
if (xop < 0x20) {
- cpu_src1 = get_src1(insn, cpu_src1);
- cpu_src2 = get_src2(insn, cpu_src2);
+ cpu_src1 = get_src1(dc, insn);
+ cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
case 0x0: /* add */
if (xop & 0x10) {
@@ -3563,8 +3546,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
gen_store_gpr(dc, rd, cpu_dst);
} else {
- cpu_src1 = get_src1(insn, cpu_src1);
- cpu_src2 = get_src2(insn, cpu_src2);
+ cpu_src1 = get_src1(dc, insn);
+ cpu_src2 = get_src2(dc, insn);
switch (xop) {
case 0x20: /* taddcc */
gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
@@ -4153,14 +4136,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x010: /* VIS I array8 */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x012: /* VIS I array16 */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
@@ -4168,7 +4151,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x014: /* VIS I array32 */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
@@ -4176,22 +4159,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x018: /* VIS I alignaddr */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x01a: /* VIS I alignaddrl */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x019: /* VIS II bmask */
CHECK_FPU_FEATURE(dc, VIS2);
- cpu_src1 = get_src1(insn, cpu_src1);
- cpu_src2 = get_src2(insn, cpu_src2);
+ cpu_src1 = gen_load_gpr(dc, rs1);
+ cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
gen_store_gpr(dc, rd, cpu_dst);
@@ -4511,7 +4494,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
TCGv_i32 r_const;
save_state(dc);
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
@@ -4534,7 +4517,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto jmp_insn;
#endif
} else {
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
@@ -4632,7 +4615,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
{
unsigned int xop = GET_FIELD(insn, 7, 12);
- cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src1 = get_src1(dc, insn);
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 04/20] target-sparc: Convert asi helpers to gen_*_gpr
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (2 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 03/20] target-sparc: Use gen_load_gpr in get_src[12] Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 05/20] target-sparc: Convert swap to gen_load/store_gpr Richard Henderson
` (16 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Push the DisasContext down so that we can use gen_load/store_gpr
in sode gen_ldda_asi, gen_stda_ast, gen_cas_asi, gen_casx_asi.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 61 +++++++++++++++++++++++++-----------------------
1 file changed, 32 insertions(+), 29 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 760cfd6..f4ab6cc 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2101,7 +2101,8 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
}
-static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
+static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
+ int insn, int rd)
{
TCGv_i32 r_asi, r_rd;
@@ -2112,12 +2113,13 @@ static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
tcg_temp_free_i32(r_asi);
}
-static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
+static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
+ int insn, int rd)
{
TCGv_i32 r_asi, r_size;
+ TCGv lo = gen_load_gpr(dc, rd + 1);
- gen_movl_reg_TN(rd + 1, cpu_tmp0);
- tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
+ tcg_gen_concat_tl_i64(cpu_tmp64, lo, hi);
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(8);
gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
@@ -2125,28 +2127,23 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
tcg_temp_free_i32(r_asi);
}
-static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
- int rd)
+static inline void gen_cas_asi(DisasContext *dc, TCGv dst, TCGv addr,
+ TCGv val2, int insn, int rd)
{
- TCGv r_val1;
- TCGv_i32 r_asi;
+ TCGv r_val1 = gen_load_gpr(dc, rd);
+ TCGv_i32 r_asi = gen_get_asi(insn, addr);
- r_val1 = tcg_temp_new();
- gen_movl_reg_TN(rd, r_val1);
- r_asi = gen_get_asi(insn, addr);
gen_helper_cas_asi(dst, cpu_env, addr, r_val1, val2, r_asi);
tcg_temp_free_i32(r_asi);
- tcg_temp_free(r_val1);
}
-static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
- int rd)
+static inline void gen_casx_asi(DisasContext *dc, TCGv dst, TCGv addr,
+ TCGv val2, int insn, int rd)
{
- TCGv_i32 r_asi;
+ TCGv r_val1 = gen_load_gpr(dc, rd);
+ TCGv_i32 r_asi = gen_get_asi(insn, addr);
- gen_movl_reg_TN(rd, cpu_tmp64);
- r_asi = gen_get_asi(insn, addr);
- gen_helper_casx_asi(dst, cpu_env, addr, cpu_tmp64, val2, r_asi);
+ gen_helper_casx_asi(dst, cpu_env, addr, r_val1, val2, r_asi);
tcg_temp_free_i32(r_asi);
}
@@ -2198,9 +2195,11 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
}
-static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
+static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
+ int insn, int rd)
{
TCGv_i32 r_asi, r_size, r_sign;
+ TCGv t;
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(8);
@@ -2209,19 +2208,23 @@ static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
tcg_temp_free(r_sign);
tcg_temp_free(r_size);
tcg_temp_free(r_asi);
- tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
- gen_movl_TN_reg(rd + 1, cpu_tmp0);
+
+ t = gen_dest_gpr(dc, rd + 1);
+ tcg_gen_trunc_i64_tl(t, cpu_tmp64);
+ gen_store_gpr(dc, rd + 1, t);
+
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
- gen_movl_TN_reg(rd, hi);
+ gen_store_gpr(dc, rd, hi);
}
-static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
+static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
+ int insn, int rd)
{
TCGv_i32 r_asi, r_size;
+ TCGv lo = gen_load_gpr(dc, rd + 1);
- gen_movl_reg_TN(rd + 1, cpu_tmp0);
- tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
+ tcg_gen_concat_tl_i64(cpu_tmp64, lo, hi);
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(8);
gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
@@ -4738,7 +4741,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (rd & 1)
goto illegal_insn;
save_state(dc);
- gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
+ gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
goto skip_move;
case 0x19: /* ldsba, load signed byte alternate */
#ifndef TARGET_SPARC64
@@ -4976,7 +4979,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
else {
save_state(dc);
- gen_stda_asi(cpu_val, cpu_addr, insn, rd);
+ gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
}
break;
#endif
@@ -5085,11 +5088,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break;
case 0x3c: /* V9 casa */
- gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
+ gen_cas_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd);
gen_store_gpr(dc, rd, cpu_val);
break;
case 0x3e: /* V9 casxa */
- gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
+ gen_casx_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd);
gen_store_gpr(dc, rd, cpu_val);
break;
#else
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 05/20] target-sparc: Convert swap to gen_load/store_gpr
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (3 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 04/20] target-sparc: Convert asi helpers to gen_*_gpr Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 06/20] target-sparc: Finish conversion to gen_load_gpr Richard Henderson
` (15 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f4ab6cc..8a2e914 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2086,7 +2086,7 @@ static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
tcg_temp_free_i32(r_asi);
}
-static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
+static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
{
TCGv_i32 r_asi, r_size, r_sign;
@@ -2095,7 +2095,7 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
r_sign = tcg_const_i32(0);
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free_i32(r_sign);
- gen_helper_st_asi(cpu_env, addr, dst, r_asi, r_size);
+ gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
@@ -2176,7 +2176,7 @@ static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
tcg_temp_free(r_asi);
}
-static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
+static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
{
TCGv_i32 r_asi, r_size, r_sign;
TCGv_i64 r_val;
@@ -2187,7 +2187,7 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free(r_sign);
r_val = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(r_val, dst);
+ tcg_gen_extu_tl_i64(r_val, src);
gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
tcg_temp_free_i64(r_val);
tcg_temp_free(r_size);
@@ -4694,10 +4694,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x0f: /* swap, swap register with memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
- gen_movl_reg_TN(rd, cpu_val);
+ cpu_src1 = gen_load_gpr(dc, rd);
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
- tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
tcg_gen_mov_tl(cpu_val, cpu_tmp0);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
@@ -4783,8 +4783,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto priv_insn;
#endif
save_state(dc);
- gen_movl_reg_TN(rd, cpu_val);
- gen_swap_asi(cpu_val, cpu_addr, insn);
+ cpu_src1 = gen_load_gpr(dc, rd);
+ gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
break;
#ifndef TARGET_SPARC64
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 06/20] target-sparc: Finish conversion to gen_load_gpr
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (4 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 05/20] target-sparc: Convert swap to gen_load/store_gpr Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 07/20] target-sparc: Cleanup cpu_src[12] allocation Richard Henderson
` (14 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
All users of gen_movl_{reg_TN,TN_reg} are removed. At the same time,
make cpu_val a local variable for load/store disassembly.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 58 +++++++++++++++++-------------------------------
1 file changed, 20 insertions(+), 38 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 8a2e914..3c9b0e3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -48,7 +48,7 @@ static TCGv cpu_y;
#ifndef CONFIG_USER_ONLY
static TCGv cpu_tbr;
#endif
-static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val;
+static TCGv cpu_cond, cpu_dst, cpu_addr;
#ifdef TARGET_SPARC64
static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
static TCGv cpu_gsr;
@@ -308,28 +308,6 @@ static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
}
}
-static inline void gen_movl_reg_TN(int reg, TCGv tn)
-{
- if (reg == 0)
- tcg_gen_movi_tl(tn, 0);
- else if (reg < 8)
- tcg_gen_mov_tl(tn, cpu_gregs[reg]);
- else {
- tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
- }
-}
-
-static inline void gen_movl_TN_reg(int reg, TCGv tn)
-{
- if (reg == 0)
- return;
- else if (reg < 8)
- tcg_gen_mov_tl(cpu_gregs[reg], tn);
- else {
- tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
- }
-}
-
static inline void gen_goto_tb(DisasContext *s, int tb_num,
target_ulong pc, target_ulong npc)
{
@@ -2127,24 +2105,28 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
tcg_temp_free_i32(r_asi);
}
-static inline void gen_cas_asi(DisasContext *dc, TCGv dst, TCGv addr,
+static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
TCGv val2, int insn, int rd)
{
- TCGv r_val1 = gen_load_gpr(dc, rd);
+ TCGv val1 = gen_load_gpr(dc, rd);
+ TCGv dst = gen_dest_gpr(dc, rd);
TCGv_i32 r_asi = gen_get_asi(insn, addr);
- gen_helper_cas_asi(dst, cpu_env, addr, r_val1, val2, r_asi);
+ gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
tcg_temp_free_i32(r_asi);
+ gen_store_gpr(dc, rd, dst);
}
-static inline void gen_casx_asi(DisasContext *dc, TCGv dst, TCGv addr,
+static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
TCGv val2, int insn, int rd)
{
- TCGv r_val1 = gen_load_gpr(dc, rd);
+ TCGv val1 = gen_load_gpr(dc, rd);
+ TCGv dst = gen_dest_gpr(dc, rd);
TCGv_i32 r_asi = gen_get_asi(insn, addr);
- gen_helper_casx_asi(dst, cpu_env, addr, r_val1, val2, r_asi);
+ gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
tcg_temp_free_i32(r_asi);
+ gen_store_gpr(dc, rd, dst);
}
#elif !defined(CONFIG_USER_ONLY)
@@ -4638,6 +4620,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
(xop > 0x17 && xop <= 0x1d ) ||
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
+ TCGv cpu_val = gen_dest_gpr(dc, rd);
+
switch (xop) {
case 0x0: /* ld, V9 lduw, load unsigned word */
gen_address_mask(dc, cpu_addr);
@@ -4903,7 +4887,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
} else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
xop == 0xe || xop == 0x1e) {
- gen_movl_reg_TN(rd, cpu_val);
+ TCGv cpu_val = gen_load_gpr(dc, rd);
+
switch (xop) {
case 0x4: /* st, store word */
gen_address_mask(dc, cpu_addr);
@@ -4922,6 +4907,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
else {
TCGv_i32 r_const;
+ TCGv lo;
save_state(dc);
gen_address_mask(dc, cpu_addr);
@@ -4929,8 +4915,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
/* XXX remove alignment check */
gen_helper_check_align(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
- gen_movl_reg_TN(rd + 1, cpu_tmp0);
- tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val);
+ lo = gen_load_gpr(dc, rd + 1);
+ tcg_gen_concat_tl_i64(cpu_tmp64, lo, cpu_val);
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
}
break;
@@ -5088,12 +5074,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break;
case 0x3c: /* V9 casa */
- gen_cas_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd);
- gen_store_gpr(dc, rd, cpu_val);
+ gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
break;
case 0x3e: /* V9 casxa */
- gen_casx_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd);
- gen_store_gpr(dc, rd, cpu_val);
+ gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
break;
#else
case 0x34: /* stc */
@@ -5269,14 +5253,12 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
cpu_tmp32 = tcg_temp_new_i32();
cpu_tmp64 = tcg_temp_new_i64();
cpu_dst = tcg_temp_new();
- cpu_val = tcg_temp_new();
cpu_addr = tcg_temp_new();
disas_sparc_insn(dc, insn);
num_insns++;
tcg_temp_free(cpu_addr);
- tcg_temp_free(cpu_val);
tcg_temp_free(cpu_dst);
tcg_temp_free_i64(cpu_tmp64);
tcg_temp_free_i32(cpu_tmp32);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 07/20] target-sparc: Cleanup cpu_src[12] allocation
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (5 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 06/20] target-sparc: Finish conversion to gen_load_gpr Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 08/20] target-sparc: Make the cpu_addr variable local to load/store handling Richard Henderson
` (13 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Now that get_temp_tl is used for get_src[12], we don't need to
pre-allocate these temporaries.
Fallout from this is moving some assignments around cas/casx to
avoid uninitialized variable warnings.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 3c9b0e3..2a95c1f 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2483,7 +2483,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
{
unsigned int opc, rs1, rs2, rd;
- TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2;
+ TCGv cpu_src1, cpu_src2;
TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
target_long simm;
@@ -2496,9 +2496,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
rd = GET_FIELD(insn, 2, 6);
- cpu_tmp1 = cpu_src1 = tcg_temp_new();
- cpu_tmp2 = cpu_src2 = tcg_temp_new();
-
switch (opc) {
case 0: /* branches/sethi */
{
@@ -4602,8 +4599,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn);
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
- rs2 = GET_FIELD(insn, 27, 31);
- cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_mov_tl(cpu_addr, cpu_src1);
} else if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
@@ -5074,9 +5069,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break;
case 0x3c: /* V9 casa */
+ rs2 = GET_FIELD(insn, 27, 31);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
break;
case 0x3e: /* V9 casxa */
+ rs2 = GET_FIELD(insn, 27, 31);
+ cpu_src2 = gen_load_gpr(dc, rs2);
gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
break;
#else
@@ -5089,8 +5088,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
default:
goto illegal_insn;
}
- } else
+ } else {
goto illegal_insn;
+ }
}
break;
}
@@ -5169,8 +5169,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto egress;
#endif
egress:
- tcg_temp_free(cpu_tmp1);
- tcg_temp_free(cpu_tmp2);
if (dc->n_t32 != 0) {
int i;
for (i = dc->n_t32 - 1; i >= 0; --i) {
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 08/20] target-sparc: Make the cpu_addr variable local to load/store handling
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (6 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 07/20] target-sparc: Cleanup cpu_src[12] allocation Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32 Richard Henderson
` (12 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 2a95c1f..e3e4256 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -48,7 +48,7 @@ static TCGv cpu_y;
#ifndef CONFIG_USER_ONLY
static TCGv cpu_tbr;
#endif
-static TCGv cpu_cond, cpu_dst, cpu_addr;
+static TCGv cpu_cond, cpu_dst;
#ifdef TARGET_SPARC64
static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
static TCGv cpu_gsr;
@@ -4596,20 +4596,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 3: /* load/store instructions */
{
unsigned int xop = GET_FIELD(insn, 7, 12);
+ /* ??? gen_address_mask prevents us from using a source
+ register directly. Always generate a temporary. */
+ TCGv cpu_addr = get_temp_tl(dc);
- cpu_src1 = get_src1(dc, insn);
- if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
- tcg_gen_mov_tl(cpu_addr, cpu_src1);
+ tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
+ if (xop == 0x3c || xop == 0x3e) {
+ /* V9 casa/casxa : no offset */
} else if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_addi_tl(cpu_addr, cpu_src1, simm);
+ if (simm != 0) {
+ tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
+ }
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 != 0) {
- cpu_src2 = gen_load_gpr(dc, rs2);
- tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
- } else {
- tcg_gen_mov_tl(cpu_addr, cpu_src1);
+ tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
}
}
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
@@ -5251,12 +5253,10 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
cpu_tmp32 = tcg_temp_new_i32();
cpu_tmp64 = tcg_temp_new_i64();
cpu_dst = tcg_temp_new();
- cpu_addr = tcg_temp_new();
disas_sparc_insn(dc, insn);
num_insns++;
- tcg_temp_free(cpu_addr);
tcg_temp_free(cpu_dst);
tcg_temp_free_i64(cpu_tmp64);
tcg_temp_free_i32(cpu_tmp32);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (7 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 08/20] target-sparc: Make the cpu_addr variable local to load/store handling Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 10/20] target-sparc: Use get_temp_i32 in gen_dest_fpr_F Richard Henderson
` (11 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index e3e4256..5296a37 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -125,6 +125,22 @@ static int sign_extend(int x, int len)
#define IS_IMM (insn & (1<<13))
+static inline TCGv_i32 get_temp_i32(DisasContext *dc)
+{
+ TCGv_i32 t;
+ assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
+ dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
+ return t;
+}
+
+static inline TCGv get_temp_tl(DisasContext *dc)
+{
+ TCGv t;
+ assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
+ dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
+ return t;
+}
+
static inline void gen_update_fprs_dirty(int rd)
{
#if defined(TARGET_SPARC64)
@@ -145,16 +161,13 @@ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
if (src & 1) {
return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
} else {
- TCGv_i32 ret = tcg_temp_new_i32();
+ TCGv_i32 ret = get_temp_i32(dc);
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
tcg_gen_trunc_i64_i32(ret, t);
tcg_temp_free_i64(t);
- dc->t32[dc->n_t32++] = ret;
- assert(dc->n_t32 <= ARRAY_SIZE(dc->t32));
-
return ret;
}
#endif
@@ -265,14 +278,6 @@ static inline void gen_address_mask(DisasContext *dc, TCGv addr)
#endif
}
-static inline TCGv get_temp_tl(DisasContext *dc)
-{
- TCGv t;
- assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
- dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
- return t;
-}
-
static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
{
if (reg == 0 || reg >= 8) {
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 10/20] target-sparc: Use get_temp_i32 in gen_dest_fpr_F
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (8 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32 Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 11/20] target-sparc: Avoid cpu_tmp32 in Read Priv Register Richard Henderson
` (10 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5296a37..5013aee 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -189,9 +189,9 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
gen_update_fprs_dirty(dst);
}
-static TCGv_i32 gen_dest_fpr_F(void)
+static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
{
- return cpu_tmp32;
+ return get_temp_i32(dc);
}
static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
@@ -1703,7 +1703,7 @@ static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
TCGv_i32 dst, src;
src = gen_load_fpr_F(dc, rs);
- dst = gen_dest_fpr_F();
+ dst = gen_dest_fpr_F(dc);
gen(dst, cpu_env, src);
@@ -1716,7 +1716,7 @@ static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
TCGv_i32 dst, src;
src = gen_load_fpr_F(dc, rs);
- dst = gen_dest_fpr_F();
+ dst = gen_dest_fpr_F(dc);
gen(dst, src);
@@ -1730,7 +1730,7 @@ static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
src1 = gen_load_fpr_F(dc, rs1);
src2 = gen_load_fpr_F(dc, rs2);
- dst = gen_dest_fpr_F();
+ dst = gen_dest_fpr_F(dc);
gen(dst, cpu_env, src1, src2);
@@ -1745,7 +1745,7 @@ static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
src1 = gen_load_fpr_F(dc, rs1);
src2 = gen_load_fpr_F(dc, rs2);
- dst = gen_dest_fpr_F();
+ dst = gen_dest_fpr_F(dc);
gen(dst, src1, src2);
@@ -1942,7 +1942,7 @@ static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
TCGv_i64 src;
src = gen_load_fpr_D(dc, rs);
- dst = gen_dest_fpr_F();
+ dst = gen_dest_fpr_F(dc);
gen(dst, cpu_env, src);
@@ -1955,7 +1955,7 @@ static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
TCGv_i32 dst;
gen_op_load_fpr_QT1(QFPREG(rs));
- dst = gen_dest_fpr_F();
+ dst = gen_dest_fpr_F(dc);
gen(dst, cpu_env);
@@ -2277,7 +2277,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
s1 = gen_load_fpr_F(dc, rs);
s2 = gen_load_fpr_F(dc, rd);
- dst = gen_dest_fpr_F();
+ dst = gen_dest_fpr_F(dc);
zero = tcg_const_i32(0);
tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
@@ -4257,14 +4257,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x03b: /* VIS I fpack16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
- cpu_dst_32 = gen_dest_fpr_F();
+ cpu_dst_32 = gen_dest_fpr_F(dc);
gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x03d: /* VIS I fpackfix */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
- cpu_dst_32 = gen_dest_fpr_F();
+ cpu_dst_32 = gen_dest_fpr_F(dc);
gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
@@ -4328,7 +4328,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x061: /* VIS I fzeros */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_dst_32 = gen_dest_fpr_F();
+ cpu_dst_32 = gen_dest_fpr_F(dc);
tcg_gen_movi_i32(cpu_dst_32, 0);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
@@ -4456,7 +4456,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x07f: /* VIS I fones */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_dst_32 = gen_dest_fpr_F();
+ cpu_dst_32 = gen_dest_fpr_F(dc);
tcg_gen_movi_i32(cpu_dst_32, -1);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
@@ -4843,7 +4843,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x20: /* ldf, load fpreg */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
- cpu_dst_32 = gen_dest_fpr_F();
+ cpu_dst_32 = gen_dest_fpr_F(dc);
tcg_gen_trunc_tl_i32(cpu_dst_32, cpu_tmp0);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 11/20] target-sparc: Avoid cpu_tmp32 in Read Priv Register
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (9 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 10/20] target-sparc: Use get_temp_i32 in gen_dest_fpr_F Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 12/20] target-sparc: Avoid cpu_tmp32 in Write " Richard Henderson
` (9 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
We don't need another temporary here. Load directly into the
register we want to set.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 53 +++++++++++++++++++-----------------------------
1 file changed, 21 insertions(+), 32 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5013aee..43e44d5 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2865,14 +2865,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 3: // tt
{
- TCGv_ptr r_tsptr;
+ TCGv_ptr r_tsptr = tcg_temp_new_ptr();
- r_tsptr = tcg_temp_new_ptr();
gen_load_trap_state_at_tl(r_tsptr, cpu_env);
- tcg_gen_ld_i32(cpu_tmp32, r_tsptr,
- offsetof(trap_state, tt));
+ tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
+ offsetof(trap_state, tt));
tcg_temp_free_ptr(r_tsptr);
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
}
break;
case 4: // tick
@@ -2890,53 +2888,44 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
break;
case 6: // pstate
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, pstate));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, pstate));
break;
case 7: // tl
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, tl));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, tl));
break;
case 8: // pil
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, psrpil));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, psrpil));
break;
case 9: // cwp
gen_helper_rdcwp(cpu_tmp0, cpu_env);
break;
case 10: // cansave
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, cansave));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, cansave));
break;
case 11: // canrestore
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, canrestore));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, canrestore));
break;
case 12: // cleanwin
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, cleanwin));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, cleanwin));
break;
case 13: // otherwin
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, otherwin));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, otherwin));
break;
case 14: // wstate
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, wstate));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, wstate));
break;
case 16: // UA2005 gl
CHECK_IU_FEATURE(dc, GL);
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, gl));
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
+ tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, gl));
break;
case 26: // UA2005 strand status
CHECK_IU_FEATURE(dc, HYPV);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 12/20] target-sparc: Avoid cpu_tmp32 in Write Priv Register
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (10 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 11/20] target-sparc: Avoid cpu_tmp32 in Read Priv Register Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 13/20] target-sparc: Tidy ldfsr, stfsr Richard Henderson
` (8 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
No need to copy to a temporary to store 32 bits.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 56 +++++++++++++++++++++---------------------------
1 file changed, 24 insertions(+), 32 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 43e44d5..353ebc6 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3801,9 +3801,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_tsptr = tcg_temp_new_ptr();
gen_load_trap_state_at_tl(r_tsptr, cpu_env);
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, r_tsptr,
- offsetof(trap_state, tt));
+ tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
+ offsetof(trap_state, tt));
tcg_temp_free_ptr(r_tsptr);
}
break;
@@ -3829,8 +3828,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 7: // tl
save_state(dc);
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
offsetof(CPUSPARCState, tl));
dc->npc = DYNAMIC_PC;
break;
@@ -3841,40 +3839,34 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_helper_wrcwp(cpu_env, cpu_tmp0);
break;
case 10: // cansave
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState,
- cansave));
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ cansave));
break;
case 11: // canrestore
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState,
- canrestore));
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ canrestore));
break;
case 12: // cleanwin
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState,
- cleanwin));
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ cleanwin));
break;
case 13: // otherwin
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState,
- otherwin));
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ otherwin));
break;
case 14: // wstate
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState,
- wstate));
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ wstate));
break;
case 16: // UA2005 gl
CHECK_IU_FEATURE(dc, GL);
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState, gl));
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, gl));
break;
case 26: // UA2005 strand status
CHECK_IU_FEATURE(dc, HYPV);
@@ -3886,11 +3878,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
}
#else
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- if (dc->def->nwindows != 32)
- tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
+ tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
+ if (dc->def->nwindows != 32) {
+ tcg_gen_andi_tl(cpu_wim, cpu_wim,
(1 << dc->def->nwindows) - 1);
- tcg_gen_mov_i32(cpu_wim, cpu_tmp32);
+ }
#endif
}
break;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 13/20] target-sparc: Tidy ldfsr, stfsr
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (11 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 12/20] target-sparc: Avoid cpu_tmp32 in Write " Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 14/20] target-sparc: Remove usage of cpu_tmp64 from most helper functions Richard Henderson
` (7 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Remove the last uses of cpu_tmp32. Unify the code between sparc64
and sparc32 by using the proper "tl" functions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 37 +++++++++++++++++--------------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 353ebc6..ed341b8 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -60,7 +60,6 @@ static TCGv cpu_wim;
#endif
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0;
-static TCGv_i32 cpu_tmp32;
static TCGv_i64 cpu_tmp64;
/* Floating point registers */
static TCGv_i64 cpu_fpr[TARGET_DPREGS];
@@ -4834,17 +4833,15 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (rd == 1) {
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
gen_helper_ldxfsr(cpu_env, cpu_tmp64);
- } else {
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- gen_helper_ldfsr(cpu_env, cpu_tmp32);
+ break;
}
-#else
+#endif
{
- tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
- gen_helper_ldfsr(cpu_env, cpu_tmp32);
+ TCGv_i32 t32 = get_temp_i32(dc);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
+ tcg_gen_trunc_tl_i32(t32, cpu_tmp0);
+ gen_helper_ldfsr(cpu_env, t32);
}
-#endif
break;
case 0x22: /* ldqf, load quad fpreg */
{
@@ -4979,17 +4976,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
break;
case 0x25: /* stfsr, V9 stxfsr */
+ {
+ TCGv t = get_temp_tl(dc);
+
+ tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
#ifdef TARGET_SPARC64
- gen_address_mask(dc, cpu_addr);
- tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUSPARCState, fsr));
- if (rd == 1)
- tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
- else
- tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
-#else
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fsr));
- tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
+ if (rd == 1) {
+ tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
+ break;
+ }
#endif
+ tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
+ }
break;
case 0x26:
#ifdef TARGET_SPARC64
@@ -5236,7 +5235,6 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
insn = cpu_ldl_code(env, dc->pc);
cpu_tmp0 = tcg_temp_new();
- cpu_tmp32 = tcg_temp_new_i32();
cpu_tmp64 = tcg_temp_new_i64();
cpu_dst = tcg_temp_new();
@@ -5245,7 +5243,6 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
tcg_temp_free(cpu_dst);
tcg_temp_free_i64(cpu_tmp64);
- tcg_temp_free_i32(cpu_tmp32);
tcg_temp_free(cpu_tmp0);
if (dc->is_br)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 14/20] target-sparc: Remove usage of cpu_tmp64 from most helper functions
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (12 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 13/20] target-sparc: Tidy ldfsr, stfsr Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 15/20] target-sparc: Don't use a temporary for gen_dest_fpr_D Richard Henderson
` (6 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Use a locally allocated temporary instead.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 73 +++++++++++++++++++++++++++++-------------------
1 file changed, 44 insertions(+), 29 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index ed341b8..9b7bbef 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2071,16 +2071,18 @@ static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
{
TCGv_i32 r_asi, r_size, r_sign;
+ TCGv_i64 t64 = tcg_temp_new_i64();
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(4);
r_sign = tcg_const_i32(0);
- gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free_i32(r_sign);
gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
- tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
+ tcg_gen_trunc_i64_tl(dst, t64);
+ tcg_temp_free_i64(t64);
}
static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
@@ -2100,13 +2102,15 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
{
TCGv_i32 r_asi, r_size;
TCGv lo = gen_load_gpr(dc, rd + 1);
+ TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat_tl_i64(cpu_tmp64, lo, hi);
+ tcg_gen_concat_tl_i64(t64, lo, hi);
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(8);
- gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
+ gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
+ tcg_temp_free_i64(t64);
}
static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
@@ -2139,46 +2143,52 @@ static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
int sign)
{
TCGv_i32 r_asi, r_size, r_sign;
+ TCGv_i64 t64 = tcg_temp_new_i64();
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(size);
r_sign = tcg_const_i32(sign);
- gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
- tcg_temp_free(r_sign);
- tcg_temp_free(r_size);
- tcg_temp_free(r_asi);
- tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
+ tcg_temp_free_i32(r_sign);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ tcg_gen_trunc_i64_tl(dst, t64);
+ tcg_temp_free_i64(t64);
}
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
{
TCGv_i32 r_asi, r_size;
+ TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(cpu_tmp64, src);
+ tcg_gen_extu_tl_i64(t64, src);
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(size);
- gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
- tcg_temp_free(r_size);
- tcg_temp_free(r_asi);
+ gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ tcg_temp_free_i64(t64);
}
static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
{
TCGv_i32 r_asi, r_size, r_sign;
- TCGv_i64 r_val;
+ TCGv_i64 r_val, t64;
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(4);
r_sign = tcg_const_i32(0);
- gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
+ t64 = tcg_temp_new_i64();
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free(r_sign);
r_val = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(r_val, src);
gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
tcg_temp_free_i64(r_val);
- tcg_temp_free(r_size);
- tcg_temp_free(r_asi);
- tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ tcg_gen_trunc_i64_tl(dst, t64);
+ tcg_temp_free_i64(t64);
}
static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
@@ -2186,21 +2196,24 @@ static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
{
TCGv_i32 r_asi, r_size, r_sign;
TCGv t;
+ TCGv_i64 t64;
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(8);
r_sign = tcg_const_i32(0);
- gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
- tcg_temp_free(r_sign);
- tcg_temp_free(r_size);
- tcg_temp_free(r_asi);
+ t64 = tcg_temp_new_i64();
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
+ tcg_temp_free_i32(r_sign);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
t = gen_dest_gpr(dc, rd + 1);
- tcg_gen_trunc_i64_tl(t, cpu_tmp64);
+ tcg_gen_trunc_i64_tl(t, t64);
gen_store_gpr(dc, rd + 1, t);
- tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
- tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
+ tcg_gen_shri_i64(t64, t64, 32);
+ tcg_gen_trunc_i64_tl(hi, t64);
+ tcg_temp_free_i64(t64);
gen_store_gpr(dc, rd, hi);
}
@@ -2209,13 +2222,15 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
{
TCGv_i32 r_asi, r_size;
TCGv lo = gen_load_gpr(dc, rd + 1);
+ TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat_tl_i64(cpu_tmp64, lo, hi);
+ tcg_gen_concat_tl_i64(t64, lo, hi);
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(8);
- gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size);
- tcg_temp_free(r_size);
- tcg_temp_free(r_asi);
+ gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ tcg_temp_free_i64(t64);
}
#endif
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 15/20] target-sparc: Don't use a temporary for gen_dest_fpr_D
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (13 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 14/20] target-sparc: Remove usage of cpu_tmp64 from most helper functions Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 16/20] target-sparc: Remove cpu_tmp64 use from softint insns Richard Henderson
` (5 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
In all cases we don't have write-before-read problems.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 9b7bbef..00ceb9d 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -206,9 +206,9 @@ static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
gen_update_fprs_dirty(dst);
}
-static TCGv_i64 gen_dest_fpr_D(void)
+static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
{
- return cpu_tmp64;
+ return cpu_fpr[DFPREG(dst) / 2];
}
static void gen_op_load_fpr_QT0(unsigned int src)
@@ -1758,7 +1758,7 @@ static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
TCGv_i64 dst, src;
src = gen_load_fpr_D(dc, rs);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, cpu_env, src);
@@ -1772,7 +1772,7 @@ static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
TCGv_i64 dst, src;
src = gen_load_fpr_D(dc, rs);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, src);
@@ -1787,7 +1787,7 @@ static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
src1 = gen_load_fpr_D(dc, rs1);
src2 = gen_load_fpr_D(dc, rs2);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, cpu_env, src1, src2);
@@ -1802,7 +1802,7 @@ static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
src1 = gen_load_fpr_D(dc, rs1);
src2 = gen_load_fpr_D(dc, rs2);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, src1, src2);
@@ -1816,7 +1816,7 @@ static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
src1 = gen_load_fpr_D(dc, rs1);
src2 = gen_load_fpr_D(dc, rs2);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, cpu_gsr, src1, src2);
@@ -1831,7 +1831,7 @@ static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
src1 = gen_load_fpr_D(dc, rs1);
src2 = gen_load_fpr_D(dc, rs2);
src0 = gen_load_fpr_D(dc, rd);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, src0, src1, src2);
@@ -1883,7 +1883,7 @@ static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
src1 = gen_load_fpr_F(dc, rs1);
src2 = gen_load_fpr_F(dc, rs2);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, cpu_env, src1, src2);
@@ -1912,7 +1912,7 @@ static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
TCGv_i32 src;
src = gen_load_fpr_F(dc, rs);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, cpu_env, src);
@@ -1927,7 +1927,7 @@ static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
TCGv_i32 src;
src = gen_load_fpr_F(dc, rs);
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, cpu_env, src);
@@ -1967,7 +1967,7 @@ static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
TCGv_i64 dst;
gen_op_load_fpr_QT1(QFPREG(rs));
- dst = gen_dest_fpr_D();
+ dst = gen_dest_fpr_D(dc, rd);
gen(dst, cpu_env);
@@ -2303,7 +2303,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
{
- TCGv_i64 dst = gen_dest_fpr_D();
+ TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
gen_load_fpr_D(dc, rs),
gen_load_fpr_D(dc, rd));
@@ -4317,7 +4317,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x060: /* VIS I fzero */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_dst_64 = gen_dest_fpr_D();
+ cpu_dst_64 = gen_dest_fpr_D(dc, rd);
tcg_gen_movi_i64(cpu_dst_64, 0);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
@@ -4445,7 +4445,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x07e: /* VIS I fone */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_dst_64 = gen_dest_fpr_D();
+ cpu_dst_64 = gen_dest_fpr_D(dc, rd);
tcg_gen_movi_i64(cpu_dst_64, -1);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
@@ -4873,7 +4873,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x23: /* lddf, load double fpreg */
gen_address_mask(dc, cpu_addr);
- cpu_dst_64 = gen_dest_fpr_D();
+ cpu_dst_64 = gen_dest_fpr_D(dc, rd);
tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 16/20] target-sparc: Remove cpu_tmp64 use from softint insns
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (14 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 15/20] target-sparc: Don't use a temporary for gen_dest_fpr_D Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 17/20] target-sparc: Remove last uses of cpu_tmp64 Richard Henderson
` (4 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
The use of "tl" functions and a tmp64 is logically incompatible.
Use cpu_tmp0 instead.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 00ceb9d..64feaa3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3655,20 +3655,20 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x14: /* Softint set */
if (!supervisor(dc))
goto illegal_insn;
- tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
- gen_helper_set_softint(cpu_env, cpu_tmp64);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ gen_helper_set_softint(cpu_env, cpu_tmp0);
break;
case 0x15: /* Softint clear */
if (!supervisor(dc))
goto illegal_insn;
- tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
- gen_helper_clear_softint(cpu_env, cpu_tmp64);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ gen_helper_clear_softint(cpu_env, cpu_tmp0);
break;
case 0x16: /* Softint write */
if (!supervisor(dc))
goto illegal_insn;
- tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
- gen_helper_write_softint(cpu_env, cpu_tmp64);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ gen_helper_write_softint(cpu_env, cpu_tmp0);
break;
case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 17/20] target-sparc: Remove last uses of cpu_tmp64
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (15 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 16/20] target-sparc: Remove cpu_tmp64 use from softint insns Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 18/20] target-sparc: Only use cpu_dst for eventual writes to a gpr Richard Henderson
` (3 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 28 +++++++++++++++++-----------
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 64feaa3..16cf8de 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -60,7 +60,6 @@ static TCGv cpu_wim;
#endif
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0;
-static TCGv_i64 cpu_tmp64;
/* Floating point registers */
static TCGv_i64 cpu_fpr[TARGET_DPREGS];
@@ -4637,6 +4636,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
else {
TCGv_i32 r_const;
+ TCGv_i64 t64;
save_state(dc);
r_const = tcg_const_i32(7);
@@ -4644,12 +4644,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_helper_check_align(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
- tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
+ t64 = tcg_temp_new_i64();
+ tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
+ tcg_gen_trunc_i64_tl(cpu_tmp0, t64);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
gen_store_gpr(dc, rd + 1, cpu_tmp0);
- tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
- tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
+ tcg_gen_shri_i64(t64, t64, 32);
+ tcg_gen_trunc_i64_tl(cpu_val, t64);
+ tcg_temp_free_i64(t64);
tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
}
break;
@@ -4846,8 +4848,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
if (rd == 1) {
- tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
- gen_helper_ldxfsr(cpu_env, cpu_tmp64);
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
+ gen_helper_ldxfsr(cpu_env, t64);
+ tcg_temp_free_i64(t64);
break;
}
#endif
@@ -4902,6 +4906,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
else {
TCGv_i32 r_const;
+ TCGv_i64 t64;
TCGv lo;
save_state(dc);
@@ -4911,8 +4916,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_helper_check_align(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
lo = gen_load_gpr(dc, rd + 1);
- tcg_gen_concat_tl_i64(cpu_tmp64, lo, cpu_val);
- tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
+
+ t64 = tcg_temp_new_i64();
+ tcg_gen_concat_tl_i64(t64, lo, cpu_val);
+ tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
+ tcg_temp_free_i64(t64);
}
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
@@ -5250,14 +5258,12 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
insn = cpu_ldl_code(env, dc->pc);
cpu_tmp0 = tcg_temp_new();
- cpu_tmp64 = tcg_temp_new_i64();
cpu_dst = tcg_temp_new();
disas_sparc_insn(dc, insn);
num_insns++;
tcg_temp_free(cpu_dst);
- tcg_temp_free_i64(cpu_tmp64);
tcg_temp_free(cpu_tmp0);
if (dc->is_br)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 18/20] target-sparc: Only use cpu_dst for eventual writes to a gpr
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (16 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 17/20] target-sparc: Remove last uses of cpu_tmp64 Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 19/20] target-sparc: Make cpu_dst local to OP=2 insns Richard Henderson
` (2 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Use cpu_tmp0 for other stuff, like Write Priv Register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 52 ++++++++++++++++++++++++------------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 16cf8de..5b7e82b 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3620,19 +3620,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
#else
case 0x2: /* V9 wrccr */
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- gen_helper_wrccr(cpu_env, cpu_dst);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ gen_helper_wrccr(cpu_env, cpu_tmp0);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
dc->cc_op = CC_OP_FLAGS;
break;
case 0x3: /* V9 wrasi */
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_andi_tl(cpu_dst, cpu_dst, 0xff);
- tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
+ tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
break;
case 0x6: /* V9 wrfprs */
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
@@ -3695,13 +3695,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
{
TCGv_ptr r_tickptr;
- tcg_gen_xor_tl(cpu_dst, cpu_src1,
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
cpu_src2);
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, stick));
gen_helper_tick_set_count(r_tickptr,
- cpu_dst);
+ cpu_tmp0);
tcg_temp_free_ptr(r_tickptr);
}
break;
@@ -3756,8 +3756,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto illegal_insn;
}
#else
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- gen_helper_wrpsr(cpu_env, cpu_dst);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ gen_helper_wrpsr(cpu_env, cpu_tmp0);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
dc->cc_op = CC_OP_FLAGS;
save_state(dc);
@@ -4478,22 +4478,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
+ tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2) {
cpu_src2 = gen_load_gpr(dc, rs2);
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
} else {
- tcg_gen_mov_tl(cpu_dst, cpu_src1);
+ tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
}
}
gen_helper_restore(cpu_env);
gen_mov_pc_npc(dc);
r_const = tcg_const_i32(3);
- gen_helper_check_align(cpu_env, cpu_dst, r_const);
+ gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
tcg_temp_free_i32(r_const);
- tcg_gen_mov_tl(cpu_npc, cpu_dst);
+ tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
dc->npc = DYNAMIC_PC;
goto jmp_insn;
#endif
@@ -4501,14 +4501,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
+ tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2) {
cpu_src2 = gen_load_gpr(dc, rs2);
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
} else {
- tcg_gen_mov_tl(cpu_dst, cpu_src1);
+ tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
}
}
switch (xop) {
@@ -4522,10 +4522,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_store_gpr(dc, rd, t);
gen_mov_pc_npc(dc);
r_const = tcg_const_i32(3);
- gen_helper_check_align(cpu_env, cpu_dst, r_const);
+ gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
tcg_temp_free_i32(r_const);
- gen_address_mask(dc, cpu_dst);
- tcg_gen_mov_tl(cpu_npc, cpu_dst);
+ gen_address_mask(dc, cpu_tmp0);
+ tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
dc->npc = DYNAMIC_PC;
}
goto jmp_insn;
@@ -4538,9 +4538,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto priv_insn;
gen_mov_pc_npc(dc);
r_const = tcg_const_i32(3);
- gen_helper_check_align(cpu_env, cpu_dst, r_const);
+ gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
tcg_temp_free_i32(r_const);
- tcg_gen_mov_tl(cpu_npc, cpu_dst);
+ tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
dc->npc = DYNAMIC_PC;
gen_helper_rett(cpu_env);
}
@@ -4554,12 +4554,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x3c: /* save */
save_state(dc);
gen_helper_save(cpu_env);
- gen_store_gpr(dc, rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_tmp0);
break;
case 0x3d: /* restore */
save_state(dc);
gen_helper_restore(cpu_env);
- gen_store_gpr(dc, rd, cpu_dst);
+ gen_store_gpr(dc, rd, cpu_tmp0);
break;
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
case 0x3e: /* V9 done/retry */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 19/20] target-sparc: Make cpu_dst local to OP=2 insns
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (17 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 18/20] target-sparc: Only use cpu_dst for eventual writes to a gpr Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 20/20] target-sparc: Remove cpu_tmp0 as a global Richard Henderson
2012-10-13 10:36 ` [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Blue Swirl
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
And initialize it such that it (may) write directly to rd.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5b7e82b..8559cc3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -48,7 +48,7 @@ static TCGv cpu_y;
#ifndef CONFIG_USER_ONLY
static TCGv cpu_tbr;
#endif
-static TCGv cpu_cond, cpu_dst;
+static TCGv cpu_cond;
#ifdef TARGET_SPARC64
static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
static TCGv cpu_gsr;
@@ -2511,7 +2511,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
opc = GET_FIELD(insn, 0, 1);
-
rd = GET_FIELD(insn, 2, 6);
switch (opc) {
@@ -2620,6 +2619,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 2: /* FPU & Logical Operations */
{
unsigned int xop = GET_FIELD(insn, 7, 12);
+ TCGv cpu_dst = gen_dest_gpr(dc, rd);
+
if (xop == 0x3a) { /* generate trap */
int cond = GET_FIELD(insn, 3, 6);
TCGv_i32 trap;
@@ -5258,12 +5259,10 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
insn = cpu_ldl_code(env, dc->pc);
cpu_tmp0 = tcg_temp_new();
- cpu_dst = tcg_temp_new();
disas_sparc_insn(dc, insn);
num_insns++;
- tcg_temp_free(cpu_dst);
tcg_temp_free(cpu_tmp0);
if (dc->is_br)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 20/20] target-sparc: Remove cpu_tmp0 as a global
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (18 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 19/20] target-sparc: Make cpu_dst local to OP=2 insns Richard Henderson
@ 2012-10-09 22:04 ` Richard Henderson
2012-10-13 10:36 ` [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Blue Swirl
20 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-09 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl
Subroutines do their own local temporary management.
Within disas_sparc_insn we limit the existance of the variable
to OP=2 insns, and delay initialization as late as is reasonable
for the specific XOP.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 200 +++++++++++++++++++++++++++--------------------
1 file changed, 115 insertions(+), 85 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 8559cc3..031284d 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -58,8 +58,6 @@ static TCGv_i32 cpu_softint;
#else
static TCGv cpu_wim;
#endif
-/* local register indexes (only used inside old micro ops) */
-static TCGv cpu_tmp0;
/* Floating point registers */
static TCGv_i64 cpu_fpr[TARGET_DPREGS];
@@ -608,9 +606,10 @@ static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
{
- TCGv r_temp, zero;
+ TCGv r_temp, zero, t0;
r_temp = tcg_temp_new();
+ t0 = tcg_temp_new();
/* old op:
if (!(env->y & 1))
@@ -628,22 +627,23 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
// env->y = (b2 << 31) | (env->y >> 1);
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31);
- tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
- tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
- tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
- tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
+ tcg_gen_shri_tl(t0, cpu_y, 1);
+ tcg_gen_andi_tl(t0, t0, 0x7fffffff);
+ tcg_gen_or_tl(t0, t0, r_temp);
+ tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
// b1 = N ^ V;
- gen_mov_reg_N(cpu_tmp0, cpu_psr);
+ gen_mov_reg_N(t0, cpu_psr);
gen_mov_reg_V(r_temp, cpu_psr);
- tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
+ tcg_gen_xor_tl(t0, t0, r_temp);
tcg_temp_free(r_temp);
// T0 = (b1 << 31) | (T0 >> 1);
// src1 = T0;
- tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
+ tcg_gen_shli_tl(t0, t0, 31);
tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
- tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
+ tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
+ tcg_temp_free(t0);
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
@@ -675,9 +675,9 @@ static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
tcg_gen_shri_i64(r_temp, r_temp2, 32);
- tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
+ tcg_gen_trunc_i64_tl(cpu_y, r_temp);
tcg_temp_free_i64(r_temp);
- tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
+ tcg_gen_andi_tl(cpu_y, cpu_y, 0xffffffff);
tcg_gen_trunc_i64_tl(dst, r_temp2);
@@ -714,27 +714,33 @@ static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
// Z | (N ^ V)
static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
{
- gen_mov_reg_N(cpu_tmp0, src);
+ TCGv t0 = tcg_temp_new();
+ gen_mov_reg_N(t0, src);
gen_mov_reg_V(dst, src);
- tcg_gen_xor_tl(dst, dst, cpu_tmp0);
- gen_mov_reg_Z(cpu_tmp0, src);
- tcg_gen_or_tl(dst, dst, cpu_tmp0);
+ tcg_gen_xor_tl(dst, dst, t0);
+ gen_mov_reg_Z(t0, src);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_temp_free(t0);
}
// N ^ V
static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
{
- gen_mov_reg_V(cpu_tmp0, src);
+ TCGv t0 = tcg_temp_new();
+ gen_mov_reg_V(t0, src);
gen_mov_reg_N(dst, src);
- tcg_gen_xor_tl(dst, dst, cpu_tmp0);
+ tcg_gen_xor_tl(dst, dst, t0);
+ tcg_temp_free(t0);
}
// C | Z
static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
{
- gen_mov_reg_Z(cpu_tmp0, src);
+ TCGv t0 = tcg_temp_new();
+ gen_mov_reg_Z(t0, src);
gen_mov_reg_C(dst, src);
- tcg_gen_or_tl(dst, dst, cpu_tmp0);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_temp_free(t0);
}
// C
@@ -771,29 +777,21 @@ static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
// !(Z | (N ^ V))
static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
{
- gen_mov_reg_N(cpu_tmp0, src);
- gen_mov_reg_V(dst, src);
- tcg_gen_xor_tl(dst, dst, cpu_tmp0);
- gen_mov_reg_Z(cpu_tmp0, src);
- tcg_gen_or_tl(dst, dst, cpu_tmp0);
+ gen_op_eval_ble(dst, src);
tcg_gen_xori_tl(dst, dst, 0x1);
}
// !(N ^ V)
static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
{
- gen_mov_reg_V(cpu_tmp0, src);
- gen_mov_reg_N(dst, src);
- tcg_gen_xor_tl(dst, dst, cpu_tmp0);
+ gen_op_eval_bl(dst, src);
tcg_gen_xori_tl(dst, dst, 0x1);
}
// !(C | Z)
static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
{
- gen_mov_reg_Z(cpu_tmp0, src);
- gen_mov_reg_C(dst, src);
- tcg_gen_or_tl(dst, dst, cpu_tmp0);
+ gen_op_eval_bleu(dst, src);
tcg_gen_xori_tl(dst, dst, 0x1);
}
@@ -843,18 +841,22 @@ static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_or_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_temp_free(t0);
}
// 1 or 2: FCC0 ^ FCC1
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_xor_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_xor_tl(dst, dst, t0);
+ tcg_temp_free(t0);
}
// 1 or 3: FCC0
@@ -868,10 +870,11 @@ static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
- tcg_gen_and_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_andc_tl(dst, dst, t0);
+ tcg_temp_free(t0);
}
// 2 or 3: FCC1
@@ -885,39 +888,46 @@ static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- tcg_gen_xori_tl(dst, dst, 0x1);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_andc_tl(dst, t0, dst);
+ tcg_temp_free(t0);
}
// 3: FCC0 & FCC1
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_and_tl(dst, dst, t0);
+ tcg_temp_free(t0);
}
// 0: !(FCC0 | FCC1)
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_or_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_or_tl(dst, dst, t0);
tcg_gen_xori_tl(dst, dst, 0x1);
+ tcg_temp_free(t0);
}
// 0 or 3: !(FCC0 ^ FCC1)
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_xor_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_xor_tl(dst, dst, t0);
tcg_gen_xori_tl(dst, dst, 0x1);
+ tcg_temp_free(t0);
}
// 0 or 2: !FCC0
@@ -932,11 +942,12 @@ static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
- tcg_gen_and_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_andc_tl(dst, dst, t0);
tcg_gen_xori_tl(dst, dst, 0x1);
+ tcg_temp_free(t0);
}
// 0 or 1: !FCC1
@@ -951,21 +962,24 @@ static inline void gen_op_eval_fble(TCGv dst, TCGv src,
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_andc_tl(dst, t0, dst);
tcg_gen_xori_tl(dst, dst, 0x1);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, cpu_tmp0);
- tcg_gen_xori_tl(dst, dst, 0x1);
+ tcg_temp_free(t0);
}
// !3: !(FCC0 & FCC1)
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
+ TCGv t0 = tcg_temp_new();
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_FCC1(t0, src, fcc_offset);
+ tcg_gen_and_tl(dst, dst, t0);
tcg_gen_xori_tl(dst, dst, 0x1);
+ tcg_temp_free(t0);
}
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
@@ -2620,6 +2634,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
{
unsigned int xop = GET_FIELD(insn, 7, 12);
TCGv cpu_dst = gen_dest_gpr(dc, rd);
+ TCGv cpu_tmp0;
if (xop == 0x3a) { /* generate trap */
int cond = GET_FIELD(insn, 3, 6);
@@ -2839,8 +2854,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_store_gpr(dc, rd, cpu_dst);
break;
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
- if (!supervisor(dc))
+ if (!supervisor(dc)) {
goto priv_insn;
+ }
+ cpu_tmp0 = get_temp_tl(dc);
#ifdef TARGET_SPARC64
rs1 = GET_FIELD(insn, 13, 17);
switch (rs1) {
@@ -3347,6 +3364,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
+ cpu_tmp0 = get_temp_tl(dc);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
} else {
@@ -3368,6 +3386,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
+ cpu_tmp0 = get_temp_tl(dc);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
@@ -3391,6 +3410,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
+ cpu_tmp0 = get_temp_tl(dc);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
@@ -3576,6 +3596,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
simm = GET_FIELDs(insn, 20, 31);
tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
} else { /* register */
+ cpu_tmp0 = get_temp_tl(dc);
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
@@ -3586,6 +3607,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
simm = GET_FIELDs(insn, 20, 31);
tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
} else { /* register */
+ cpu_tmp0 = get_temp_tl(dc);
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
@@ -3596,6 +3618,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
simm = GET_FIELDs(insn, 20, 31);
tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
} else { /* register */
+ cpu_tmp0 = get_temp_tl(dc);
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
@@ -3604,6 +3627,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#endif
case 0x30:
{
+ cpu_tmp0 = get_temp_tl(dc);
switch(rd) {
case 0: /* wry */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
@@ -4477,6 +4501,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
cpu_src1 = get_src1(dc, insn);
+ cpu_tmp0 = get_temp_tl(dc);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
@@ -4500,6 +4525,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#endif
} else {
cpu_src1 = get_src1(dc, insn);
+ cpu_tmp0 = get_temp_tl(dc);
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
@@ -4647,13 +4673,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_address_mask(dc, cpu_addr);
t64 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
- tcg_gen_trunc_i64_tl(cpu_tmp0, t64);
- tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
- gen_store_gpr(dc, rd + 1, cpu_tmp0);
+ tcg_gen_trunc_i64_tl(cpu_val, t64);
+ tcg_gen_ext32u_tl(cpu_val, cpu_val);
+ gen_store_gpr(dc, rd + 1, cpu_val);
tcg_gen_shri_i64(t64, t64, 32);
tcg_gen_trunc_i64_tl(cpu_val, t64);
tcg_temp_free_i64(t64);
- tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
+ tcg_gen_ext32u_tl(cpu_val, cpu_val);
}
break;
case 0x9: /* ldsb, load signed byte */
@@ -4675,14 +4701,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_temp_free(r_const);
}
break;
- case 0x0f: /* swap, swap register with memory. Also
- atomically */
- CHECK_IU_FEATURE(dc, SWAP);
- cpu_src1 = gen_load_gpr(dc, rd);
- gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
- tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
- tcg_gen_mov_tl(cpu_val, cpu_tmp0);
+ case 0x0f:
+ /* swap, swap register with memory. Also atomically */
+ {
+ TCGv t0 = get_temp_tl(dc);
+ CHECK_IU_FEATURE(dc, SWAP);
+ cpu_src1 = gen_load_gpr(dc, rd);
+ gen_address_mask(dc, cpu_addr);
+ tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
+ tcg_gen_mov_tl(cpu_val, t0);
+ }
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x10: /* lda, V9 lduwa, load word alternate */
@@ -4833,6 +4862,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
skip_move: ;
#endif
} else if (xop >= 0x20 && xop < 0x24) {
+ TCGv t0;
+
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
@@ -4840,9 +4871,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
switch (xop) {
case 0x20: /* ldf, load fpreg */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
+ t0 = get_temp_tl(dc);
+ tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
cpu_dst_32 = gen_dest_fpr_F(dc);
- tcg_gen_trunc_tl_i32(cpu_dst_32, cpu_tmp0);
+ tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x21: /* ldfsr, V9 ldxfsr */
@@ -4856,12 +4888,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
}
#endif
- {
- TCGv_i32 t32 = get_temp_i32(dc);
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
- tcg_gen_trunc_tl_i32(t32, cpu_tmp0);
- gen_helper_ldfsr(cpu_env, t32);
- }
+ cpu_dst_32 = get_temp_i32(dc);
+ t0 = get_temp_tl(dc);
+ tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
+ tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
+ gen_helper_ldfsr(cpu_env, cpu_dst_32);
break;
case 0x22: /* ldqf, load quad fpreg */
{
@@ -4994,10 +5025,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
switch (xop) {
case 0x24: /* stf, store fpreg */
- gen_address_mask(dc, cpu_addr);
- cpu_src1_32 = gen_load_fpr_F(dc, rd);
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_src1_32);
- tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
+ {
+ TCGv t = get_temp_tl(dc);
+ gen_address_mask(dc, cpu_addr);
+ cpu_src1_32 = gen_load_fpr_F(dc, rd);
+ tcg_gen_ext_i32_tl(t, cpu_src1_32);
+ tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
+ }
break;
case 0x25: /* stfsr, V9 stxfsr */
{
@@ -5258,13 +5292,9 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
last_pc = dc->pc;
insn = cpu_ldl_code(env, dc->pc);
- cpu_tmp0 = tcg_temp_new();
-
disas_sparc_insn(dc, insn);
num_insns++;
- tcg_temp_free(cpu_tmp0);
-
if (dc->is_br)
break;
/* if the next PC is different, we abort now */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
` (19 preceding siblings ...)
2012-10-09 22:04 ` [Qemu-devel] [PATCH 20/20] target-sparc: Remove cpu_tmp0 as a global Richard Henderson
@ 2012-10-13 10:36 ` Blue Swirl
20 siblings, 0 replies; 23+ messages in thread
From: Blue Swirl @ 2012-10-13 10:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, Oct 9, 2012 at 10:04 PM, Richard Henderson <rth@twiddle.net> wrote:
> The primary goal of this patch set is to have all references to windowed
> registers to go through new routines that have access to DisasContext.
> This is a prerequisite to any change in how windowed registers might be
> managed.
>
> Since such a goal must of course touch get_src[12], and therefore touch
> the use of the cpu_src[12] temporaries, a secondary goal of the patch set
> became to clean up all of the temporary management within the translator.
> And in particular eliminate the 6 "global" temps that we currently allocate
> inside gen_intermediate_code_internal.
>
> In some cases we convert their uses to simple temps allocated and freed
> nearby their uses. In some cases we push the cpu_foo temp down into the
> disassembly of a given opcode, making it local to the code that ought to
> be able to access it. And finally we provide for temps to be allocated
> dynamically, and then automatically freed at the end of the insn.
I'm getting compile errors, here's Clang version.
CC sparc-softmmu/target-sparc/translate.o
/src/qemu/target-sparc/translate.c:3784:44: error: variable 'cpu_tmp0'
is uninitialized when used here [-Werror,-Wuninitialized]
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
^~~~~~~~
/src/qemu/target-sparc/translate.c:2637:26: note: initialize the
variable 'cpu_tmp0' to silence this warning
TCGv cpu_tmp0;
^
= 0
CC sparc64-softmmu/target-sparc/translate.o
/src/qemu/target-sparc/translate.c:3799:44: error: variable 'cpu_tmp0'
is uninitialized when used here [-Werror,-Wuninitialized]
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
^~~~~~~~
/src/qemu/target-sparc/translate.c:2637:26: note: initialize the
variable 'cpu_tmp0' to silence this warning
TCGv cpu_tmp0;
^
= 0
>
> The result ought to be microscopically faster than before, if only
> because TCG is iterating over fewer temporaries.
>
>
> r~
>
>
> Richard Henderson (20):
> target-sparc: Add gen_load/store/dest_gpr
> target-sparc: Conversion to gen_*_gpr, part 1
> target-sparc: Use gen_load_gpr in get_src[12]
> target-sparc: Convert asi helpers to gen_*_gpr
> target-sparc: Convert swap to gen_load/store_gpr
> target-sparc: Finish conversion to gen_load_gpr
> target-sparc: Cleanup cpu_src[12] allocation
> target-sparc: Make the cpu_addr variable local to load/store handling
> target-sparc: Split out get_temp_i32
> target-sparc: Use get_temp_i32 in gen_dest_fpr_F
> target-sparc: Avoid cpu_tmp32 in Read Priv Register
> target-sparc: Avoid cpu_tmp32 in Write Priv Register
> target-sparc: Tidy ldfsr, stfsr
> target-sparc: Remove usage of cpu_tmp64 from most helper functions
> target-sparc: Don't use a temporary for gen_dest_fpr_D
> target-sparc: Remove cpu_tmp64 use from softint insns
> target-sparc: Remove last uses of cpu_tmp64
> target-sparc: Only use cpu_dst for eventual writes to a gpr
> target-sparc: Make cpu_dst local to OP=2 insns
> target-sparc: Remove cpu_tmp0 as a global
>
> target-sparc/translate.c | 1233 +++++++++++++++++++++++-----------------------
> 1 file changed, 609 insertions(+), 624 deletions(-)
>
> --
> 1.7.11.4
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 05/20] target-sparc: Convert swap to gen_load/store_gpr
2012-10-16 9:32 [Qemu-devel] [PATCH v2 " Richard Henderson
@ 2012-10-16 9:32 ` Richard Henderson
0 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2012-10-16 9:32 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f4ab6cc..8a2e914 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2086,7 +2086,7 @@ static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
tcg_temp_free_i32(r_asi);
}
-static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
+static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
{
TCGv_i32 r_asi, r_size, r_sign;
@@ -2095,7 +2095,7 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
r_sign = tcg_const_i32(0);
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free_i32(r_sign);
- gen_helper_st_asi(cpu_env, addr, dst, r_asi, r_size);
+ gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
tcg_temp_free_i32(r_size);
tcg_temp_free_i32(r_asi);
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
@@ -2176,7 +2176,7 @@ static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
tcg_temp_free(r_asi);
}
-static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
+static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
{
TCGv_i32 r_asi, r_size, r_sign;
TCGv_i64 r_val;
@@ -2187,7 +2187,7 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
gen_helper_ld_asi(cpu_tmp64, cpu_env, addr, r_asi, r_size, r_sign);
tcg_temp_free(r_sign);
r_val = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(r_val, dst);
+ tcg_gen_extu_tl_i64(r_val, src);
gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
tcg_temp_free_i64(r_val);
tcg_temp_free(r_size);
@@ -4694,10 +4694,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x0f: /* swap, swap register with memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
- gen_movl_reg_TN(rd, cpu_val);
+ cpu_src1 = gen_load_gpr(dc, rd);
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
- tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
tcg_gen_mov_tl(cpu_val, cpu_tmp0);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
@@ -4783,8 +4783,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto priv_insn;
#endif
save_state(dc);
- gen_movl_reg_TN(rd, cpu_val);
- gen_swap_asi(cpu_val, cpu_addr, insn);
+ cpu_src1 = gen_load_gpr(dc, rd);
+ gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
break;
#ifndef TARGET_SPARC64
--
1.7.11.7
^ permalink raw reply related [flat|nested] 23+ messages in thread
end of thread, other threads:[~2012-10-16 9:33 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-10-09 22:04 [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 02/20] target-sparc: Conversion to gen_*_gpr, part 1 Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 03/20] target-sparc: Use gen_load_gpr in get_src[12] Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 04/20] target-sparc: Convert asi helpers to gen_*_gpr Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 05/20] target-sparc: Convert swap to gen_load/store_gpr Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 06/20] target-sparc: Finish conversion to gen_load_gpr Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 07/20] target-sparc: Cleanup cpu_src[12] allocation Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 08/20] target-sparc: Make the cpu_addr variable local to load/store handling Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32 Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 10/20] target-sparc: Use get_temp_i32 in gen_dest_fpr_F Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 11/20] target-sparc: Avoid cpu_tmp32 in Read Priv Register Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 12/20] target-sparc: Avoid cpu_tmp32 in Write " Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 13/20] target-sparc: Tidy ldfsr, stfsr Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 14/20] target-sparc: Remove usage of cpu_tmp64 from most helper functions Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 15/20] target-sparc: Don't use a temporary for gen_dest_fpr_D Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 16/20] target-sparc: Remove cpu_tmp64 use from softint insns Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 17/20] target-sparc: Remove last uses of cpu_tmp64 Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 18/20] target-sparc: Only use cpu_dst for eventual writes to a gpr Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 19/20] target-sparc: Make cpu_dst local to OP=2 insns Richard Henderson
2012-10-09 22:04 ` [Qemu-devel] [PATCH 20/20] target-sparc: Remove cpu_tmp0 as a global Richard Henderson
2012-10-13 10:36 ` [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps Blue Swirl
-- strict thread matches above, loose matches on Subject: below --
2012-10-16 9:32 [Qemu-devel] [PATCH v2 " Richard Henderson
2012-10-16 9:32 ` [Qemu-devel] [PATCH 05/20] target-sparc: Convert swap to gen_load/store_gpr Richard Henderson
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