From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33271) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMdZs-0000bi-Sa for qemu-devel@nongnu.org; Fri, 12 Oct 2012 07:38:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TMdZm-000826-TL for qemu-devel@nongnu.org; Fri, 12 Oct 2012 07:38:52 -0400 Received: from 38.0.169.217.in-addr.arpa ([217.169.0.38]:57335 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMdZm-00080H-N3 for qemu-devel@nongnu.org; Fri, 12 Oct 2012 07:38:46 -0400 From: Peter Maydell Date: Fri, 12 Oct 2012 12:38:24 +0100 Message-Id: <1350041912-12595-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1350041912-12595-1-git-send-email-peter.maydell@linaro.org> References: <1350041912-12595-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 1/9] cadence_ttc: Fix 'clear on read' behavior List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org, Paul Brook From: Soren Brinkmann A missing call to qemu_set_irq() when reading the IRQ register required SW to write to the IRQ register to acknowledge an interrupt. With this patch the behavior is fixed: - Reading the interrupt register clears it and updates the timers interrupt status - Writes to the interrupt register are ignored Signed-off-by: Soren Brinkmann Signed-off-by: Peter Crosthwaite Signed-off-by: Peter Maydell --- hw/cadence_ttc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c index dd02f86..77b6976 100644 --- a/hw/cadence_ttc.c +++ b/hw/cadence_ttc.c @@ -274,6 +274,7 @@ static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset) /* cleared after read */ value = s->reg_intr; s->reg_intr = 0; + cadence_timer_update(s); return value; case 0x60: /* interrupt enable */ @@ -355,7 +356,6 @@ static void cadence_ttc_write(void *opaque, target_phys_addr_t offset, case 0x54: /* interrupt register */ case 0x58: case 0x5c: - s->reg_intr &= (~value & 0xfff); break; case 0x60: /* interrupt enable */ -- 1.7.9.5