From: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Subject: [Qemu-devel] [PATCH] target-arm/translate: Fix RRX operands
Date: Tue, 16 Oct 2012 19:15:50 +1000 [thread overview]
Message-ID: <1350378950-10614-1-git-send-email-peter.crosthwaite@xilinx.com> (raw)
Instructions that both use the RRX second operand and update CS were
incorrect, as the Carry flag was updated too early. An example of such an
instruction would be:
ands r12,r13,RRX
Ands, because of the "s" flag will update the carry flag. But the RRX second
operand rotates through the C flag which should happen before the update.
Fixed the ordering of the two, the old carry is read by "r13,RRX" before being
updated.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: Vinesh Peringat <vineshp@xilinx.com>
---
target-arm/translate.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c6840b7..daccb15 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -516,10 +516,10 @@ static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
tcg_gen_rotri_i32(var, var, shift); break;
} else {
TCGv tmp = tcg_temp_new_i32();
+ tcg_gen_shli_i32(tmp, cpu_CF, 31);
if (flags)
shifter_out_im(var, 0);
tcg_gen_shri_i32(var, var, 1);
- tcg_gen_shli_i32(tmp, cpu_CF, 31);
tcg_gen_or_i32(var, var, tmp);
tcg_temp_free_i32(tmp);
}
--
1.7.0.4
next reply other threads:[~2012-10-16 9:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-16 9:15 Peter Crosthwaite [this message]
2012-10-17 16:43 ` [Qemu-devel] [PATCH] target-arm/translate: Fix RRX operands Peter Maydell
2012-10-17 18:03 ` Aurelien Jarno
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